Modeling the Impact of Phonon Scattering with Strain Effects on the Electrical Properties of MoS2 Field-Effect Transistors.

Molybdenum disulfide (MoS2) has distinctive electronic and mechanical properties which make it a highly prospective material for use as a channel in upcoming nanoelectronic devices. An analytical modeling framework was used to investigate the I-V characteristics of field-effect transistors based on MoS2. The study begins by developing a ballistic current equation using a circuit model with two contacts. The transmission probability, which considers both the acoustic and optical mean free path, is then derived. Next, the effect of phonon scattering on the device was examined by including transmission probabilities into the ballistic current equation. According to the findings, the presence of phonon scattering caused a decrease of 43.7% in the ballistic current of the device at room temperature when L = 10 nm. The influence of phonon scattering became more prominent as the temperature increased. In addition, this study also considers the impact of strain on the device. It is reported that applying compressive strain could increase the phonon scattering current by 13.3% at L = 10 nm at room temperature, as evaluated in terms of the electrons' effective masses. However, the phonon scattering current decreased by 13.3% under the same condition due to the existence of tensile strain. Moreover, incorporating a high-k dielectric to mitigate the impact of scattering resulted in an even greater improvement in device performance. Specifically, at L = 6 nm, the ballistic current was surpassed by 58.4%. Furthermore, the study achieved SS = 68.2 mV/dec using Al2O3 and an on-off ratio of 7.75 × 104 using HfO2. Finally, the analytical results were validated with previous works, showing comparable agreement with the existing literature.

Device performances analysis of p-type doped silicene-based field effect transistor using SPICE-compatible model.

Moore's Law is approaching its end as transistors are scaled down to tens or few atoms per device, researchers are actively seeking for alternative approaches to leverage more-than-Moore nanoelectronics. Substituting the channel material of a field-effect transistors (FET) with silicene is foreseen as a viable approach for future transistor applications. In this study, we proposed a SPICE-compatible model for p-type (Aluminium) uniformly doped silicene FET for digital switching applications. The performance of the proposed device is benchmarked with various low-dimensional FETs in terms of their on-to-off current ratio, subthreshold swing and drain-induced barrier lowering. The results show that the proposed p-type silicene FET is comparable to most of the selected low-dimensional FET models. With its decent performance, the proposed SPICE-compatible model should be extended to the circuit-level simulation and beyond in future work.

Semi-analytical modelling and evaluation of uniformly doped silicene nanotransistors for digital logic gates.

Silicene has attracted remarkable attention in the semiconductor research community due to its silicon (Si) nature. It is predicted as one of the most promising candidates for the next generation nanoelectronic devices. In this paper, an efficient non-iterative technique is employed to create the SPICE models for p-type and n-type uniformly doped silicene field-effect transistors (FETs). The current-voltage characteristics show that the proposed silicene FET models exhibit high on-to-off current ratio under ballistic transport. In order to obtain practical digital logic timing diagrams, a parasitic load capacitance, which is dependent on the interconnect length, is attached at the output terminal of the logic circuits. Furthermore, the key circuit performance metrics, including the propagation delay, average power, power-delay product and energy-delay product of the proposed silicene-based logic gates are extracted and benchmarked with published results. The effects of the interconnect length to the propagation delay and average power are also investigated. The results of this work further envisage the uniformly doped silicene as a promising candidate for future nanoelectronic applications.

Metal oxide-graphene field-effect transistor: interface trap density extraction model.

A simple to implement model is presented to extract interface trap density of graphene field effect transistors. The presence of interface trap states detrimentally affects the device drain current-gate voltage relationship Ids-Vgs. At the moment, there is no analytical method available to extract the interface trap distribution of metal-oxide-graphene field effect transistor (MOGFET) devices. The model presented here extracts the interface trap distribution of MOGFET devices making use of available experimental capacitance-gate voltage Ctot-Vgs data and a basic set of equations used to define the device physics of MOGFET devices. The model was used to extract the interface trap distribution of 2 experimental devices. Device parameters calculated using the extracted interface trap distribution from the model, including surface potential, interface trap charge and interface trap capacitance compared very well with their respective experimental counterparts. The model enables accurate calculation of the surface potential affected by trap charge. Other models ignore the effect of trap charge and only calculate the ideal surface potential. Such ideal surface potential when used in a surface potential based drain current model will result in an inaccurate prediction of the drain current. Accurate calculation of surface potential that can later be used in drain current model is highlighted as a major advantage of the model.

Analytical modeling of glucose biosensors based on carbon nanotubes.

In recent years, carbon nanotubes have received widespread attention as promising carbon-based nanoelectronic devices. Due to their exceptional physical, chemical, and electrical properties, namely a high surface-to-volume ratio, their enhanced electron transfer properties, and their high thermal conductivity, carbon nanotubes can be used effectively as electrochemical sensors. The integration of carbon nanotubes with a functional group provides a good and solid support for the immobilization of enzymes. The determination of glucose levels using biosensors, particularly in the medical diagnostics and food industries, is gaining mass appeal. Glucose biosensors detect the glucose molecule by catalyzing glucose to gluconic acid and hydrogen peroxide in the presence of oxygen. This action provides high accuracy and a quick detection rate. In this paper, a single-wall carbon nanotube field-effect transistor biosensor for glucose detection is analytically modeled. In the proposed model, the glucose concentration is presented as a function of gate voltage. Subsequently, the proposed model is compared with existing experimental data. A good consensus between the model and the experimental data is reported. The simulated data demonstrate that the analytical model can be employed with an electrochemical glucose sensor to predict the behavior of the sensing mechanism in biosensors.

Device and circuit-level performance of carbon nanotube field-effect transistor with benchmarking against a nano-MOSFET.

The performance of a semiconducting carbon nanotube (CNT) is assessed and tabulated for parameters against those of a metal-oxide-semiconductor field-effect transistor (MOSFET). Both CNT and MOSFET models considered agree well with the trends in the available experimental data. The results obtained show that nanotubes can significantly reduce the drain-induced barrier lowering effect and subthreshold swing in silicon channel replacement while sustaining smaller channel area at higher current density. Performance metrics of both devices such as current drive strength, current on-off ratio (Ion/Ioff), energy-delay product, and power-delay product for logic gates, namely NAND and NOR, are presented. Design rules used for carbon nanotube field-effect transistors (CNTFETs) are compatible with the 45-nm MOSFET technology. The parasitics associated with interconnects are also incorporated in the model. Interconnects can affect the propagation delay in a CNTFET. Smaller length interconnects result in higher cutoff frequency.