Acoustic-driven magnetic skyrmion motion.

Magnetic skyrmions have great potential for developing novel spintronic devices. The electrical manipulation of skyrmions has mainly relied on current-induced spin-orbit torques. Recently, it was suggested that the skyrmions could be more efficiently manipulated by surface acoustic waves (SAWs), an elastic wave that can couple with magnetic moment via the magnetoelastic effect. Here, by designing on-chip piezoelectric transducers that produce propagating SAW pulses, we experimentally demonstrate the directional motion of Néel-type skyrmions in Ta/CoFeB/MgO/Ta multilayers. We find that the shear horizontal wave effectively drives the motion of skyrmions, whereas the elastic wave with longitudinal and shear vertical displacements (Rayleigh wave) cannot produce the motion of skyrmions. A longitudinal motion along the SAW propagation direction and a transverse motion due to topological charge are simultaneously observed and further confirmed by our micromagnetic simulations. This work demonstrates that acoustic waves could be another promising approach for manipulating skyrmions, which could offer new opportunities for ultra-low power skyrmionics.

Monolithic three-dimensional integration of RRAM-based hybrid memory architecture for one-shot learning.

In this work, we report the monolithic three-dimensional integration (M3D) of hybrid memory architecture based on resistive random-access memory (RRAM), named M3D-LIME. The chip featured three key functional layers: the first was Si complementary metal-oxide-semiconductor (CMOS) for control logic; the second was computing-in-memory (CIM) layer with HfAlOx-based analog RRAM array to implement neural networks for feature extractions; the third was on-chip buffer and ternary content-addressable memory (TCAM) array for template storing and matching, based on Ta2O5-based binary RRAM and carbon nanotube field-effect transistor (CNTFET). Extensive structural analysis along with array-level electrical measurements and functional demonstrations on the CIM and TCAM arrays was performed. The M3D-LIME chip was further used to implement one-shot learning, where ~96% accuracy was achieved on the Omniglot dataset while exhibiting 18.3× higher energy efficiency than graphics processing unit (GPU). This work demonstrates the tremendous potential of M3D-LIME with RRAM-based hybrid memory architecture for future data-centric applications.

A low-power vertical dual-gate neurotransistor with short-term memory for high energy-efficient neuromorphic computing.

Neuromorphic computing aims to emulate the computing processes of the brain by replicating the functions of biological neural networks using electronic counterparts. One promising approach is dendritic computing, which takes inspiration from the multi-dendritic branch structure of neurons to enhance the processing capability of artificial neural networks. While there has been a recent surge of interest in implementing dendritic computing using emerging devices, achieving artificial dendrites with throughputs and energy efficiency comparable to those of the human brain has proven challenging. In this study, we report on the development of a compact and low-power neurotransistor based on a vertical dual-gate electrolyte-gated transistor (EGT) with short-term memory characteristics, a 30 nm channel length, a record-low read power of ~3.16 fW and a biology-comparable read energy of ~30 fJ. Leveraging this neurotransistor, we demonstrate dendrite integration as well as digital and analog dendritic computing for coincidence detection. We also showcase the potential of neurotransistors in realizing advanced brain-like functions by developing a hardware neural network and demonstrating bio-inspired sound localization. Our results suggest that the neurotransistor-based approach may pave the way for next-generation neuromorphic computing with energy efficiency on par with those of the brain.

Edge learning using a fully integrated neuro-inspired memristor chip.

Learning is highly important for edge intelligence devices to adapt to different application scenes and owners. Current technologies for training neural networks require moving massive amounts of data between computing and memory units, which hinders the implementation of learning on edge devices. We developed a fully integrated memristor chip with the improvement learning ability and low energy cost. The schemes in the STELLAR architecture, including its learning algorithm, hardware realization, and parallel conductance tuning scheme, are general approaches that facilitate on-chip learning by using a memristor crossbar array, regardless of the type of memristor device. Tasks executed in this study included motion control, image classification, and speech recognition.

Monolithic 3D Integration of Analog RRAM-Based Computing-in-Memory and Sensor for Energy-Efficient Near-Sensor Computing.

In the era of the Internet of Things, vast amounts of data generated at sensory nodes impose critical challenges on the data-transfer bandwidth and energy efficiency of computing hardware. A near-sensor computing (NSC) architecture places the processing units closer to the sensors such that the generated data can be processed almost in situ with high efficiency. This study demonstrates the monolithic three-dimensional (M3D) integration of a photosensor array, analog computing-in-memory (CIM), and Si complementary metal-oxide-semiconductor (CMOS) logic circuits, named M3D-SAIL. This approach exploits the high-bandwidth on-chip data transfer and massively parallel CIM cores to realize an energy-efficient NSC architecture. The 1st layer of the Si CMOS circuits serves as the control logic and peripheral circuits. The 2nd layer comprises a 1 k-bit one-transistor-one-resistor (1T1R) array with InGaZnOx field-effect transistor (IGZO-FET) and resistive random-access memory (RRAM) for analog CIM. The 3rd layer comprises multiple IGZO-FET-based photosensor arrays for wavelength-dependent optical sensing. The structural integrity and function of each layer are comprehensively verified. Furthermore, NSC is implemented using the M3D-SAIL architecture for a typical video keyframe-extraction task, achieving a high classification accuracy of 96.7% as well as a 31.5× lower energy consumption and 1.91× faster computing speed compared to its 2D counterpart.

Nanoscale multistate resistive switching in WO3 through scanning probe induced proton evolution.

Multistate resistive switching device emerges as a promising electronic unit for energy-efficient neuromorphic computing. Electric-field induced topotactic phase transition with ionic evolution represents an important pathway for this purpose, which, however, faces significant challenges in device scaling. This work demonstrates a convenient scanning-probe-induced proton evolution within WO3, driving a reversible insulator-to-metal transition (IMT) at nanoscale. Specifically, the Pt-coated scanning probe serves as an efficient hydrogen catalysis probe, leading to a hydrogen spillover across the nano junction between the probe and sample surface. A positively biased voltage drives protons into the sample, while a negative voltage extracts protons out, giving rise to a reversible manipulation on hydrogenation-induced electron doping, accompanied by a dramatic resistive switching. The precise control of the scanning probe offers the opportunity to manipulate the local conductivity at nanoscale, which is further visualized through a printed portrait encoded by local conductivity. Notably, multistate resistive switching is successfully demonstrated via successive set and reset processes. Our work highlights the probe-induced hydrogen evolution as a new direction to engineer memristor at nanoscale.

Energy-efficient high-fidelity image reconstruction with memristor arrays for medical diagnosis.

Medical imaging is an important tool for accurate medical diagnosis, while state-of-the-art image reconstruction algorithms raise critical challenges in massive data processing for high-speed and high-quality imaging. Here, we present a memristive image reconstructor (MIR) to greatly accelerate image reconstruction with discrete Fourier transformation (DFT) by computing-in-memory (CIM) with memristor arrays. A high-accuracy quasi-analogue mapping (QAM) method and generic complex matrix transfer (CMT) scheme was proposed to improve the mapping precision and transfer efficiency, respectively. High-fidelity magnetic resonance imaging (MRI) and computed tomography (CT) image reconstructions were demonstrated, achieving software-equivalent qualities and DICE scores after segmentation with nnU-Net algorithm. Remarkably, our MIR exhibited 153× and 79× improvements in energy efficiency and normalized image reconstruction speed, respectively, compared to graphics processing unit (GPU). This work demonstrates MIR as a promising high-fidelity image reconstruction platform for future medical diagnosis, and also largely extends the application of memristor-based CIM beyond artificial neural networks.

A Memristors-Based Dendritic Neuron for High-Efficiency Spatial-Temporal Information Processing.

Diverse microscopic ionic dynamics help mediate the ability of a biological neural network to handle complex tasks with low energy consumption. Thus, rich internal ionic dynamics in memristors based on transition metal oxide are expected to provide a unique and useful platform for implementing energy-efficient neuromorphic computing. To this end, a titanium oxide (TiOx )-based interface-type dynamic memristor and an niobium oxide (NbOx )-based Mott memristor are integrated as an artificial dendrite and spike-firing soma, respectively, to construct a dendritic neuron unit for realizing high-efficiency spatial-temporal information processing. Further, a dendritic neural network is hardware-implemented for spatial-temporal information processing to highlight the computational advantages achieved by incorporating dendritic functions in the network. Human motion recognition is demonstrated using the Nanyang Technological University-Red Green Blue (NTU-RGB) dataset as a benchmark spatial-temporal task; it shows a nearly 20% improvement in accuracy for the memristors-based hardware incorporating dendrites and a 1000× advantage in power efficiency compared to that of the graphics processing unit (GPU). The dendritic neuron developed in this study can be considered a critical building block for implementing more bio-plausible neural networks that can manage complex spatial-temporal tasks with high efficiency.

Three-Dimensional Reconstruction of Conductive Filaments in HfOx -Based Memristor.

HfOx -based memristor has been studied extensively as one of the most promising memories for the excellent nonvolatile data storage and computing-in-memory capabilities. However, the resistive switching mechanism, relying on the formation and rupture of conductive filaments (CFs) during device operations, is still under debate. In this work, the CFs with different morphologies after different operations-forming, set, and reset-are clearly revealed for the first time by 3D reconstruction of conductive atomic force microscopy (c-AFM) images. Intriguingly, multiple CFs are successfully observed in HfOx -based memristor devices with three different resistive states. CFs after forming, set, and reset exhibit the typical morphologies of hourglass, inverted-cone, and short-cone, respectively. The rupture location of CFs after the reset operation is also observed clearly. These findings reveal the microscopic behaviors underlying the resistive switching, which could pave the road to design and optimize oxide-based memristors for both memory and computing applications.

Large-Scale Integrated Flexible Tactile Sensor Array for Sensitive Smart Robotic Touch.

In the long pursuit of smart robotics, it has been envisioned to empower robots with human-like senses, especially vision and touch. While tremendous progress has been made in image sensors and computer vision over the past decades, tactile sense abilities are lagging behind due to the lack of large-scale flexible tactile sensor array with high sensitivity, high spatial resolution, and fast response. In this work, we have demonstrated a 64 × 64 flexible tactile sensor array with a record-high spatial resolution of 0.9 mm (equivalently 28.2 pixels per inch) by integrating a high-performance piezoresistive film (PRF) with a large-area active matrix of carbon nanotube thin-film transistors. PRF with self-formed microstructures exhibited high pressure-sensitivity of ∼385 kPa-1 for multi-walled carbon nanotubes concentration of 6%, while the 14% one exhibited fast response time of ∼3 ms, good linearity, broad detection range beyond 1400 kPa, and excellent cyclability over 3000 cycles. Using this fully integrated tactile sensor array, the footprint maps of an artificial honeybee were clearly identified. Furthermore, we hardware-implemented a smart tactile system by integrating the PRF-based sensor array with a memristor-based computing-in-memory chip to record and recognize handwritten digits and Chinese calligraphy, achieving high classification accuracies of 98.8% and 97.3% in hardware, respectively. The integration of sensor networks with deep learning hardware may enable edge or near-sensor computing with significantly reduced power consumption and latency. Our work could empower the building of large-scale intelligent sensor networks for next-generation smart robotics.

Concealable physically unclonable function chip with a memristor array.

A physically unclonable function (PUF) is a creditable and lightweight solution to the mistrust in billions of Internet of Things devices. Because of this remarkable importance, PUF need to be immune to multifarious attack means. Making the PUF concealable is considered an effective countermeasure but it is not feasible for existing PUF designs. The bottleneck is finding a reproducible randomness source that supports repeatable concealment and accurate recovery of the PUF data. In this work, we experimentally demonstrate a concealable PUF at the chip level with an integrated memristor array and peripherals. The correlated filamentary switching characteristic of the hafnium oxide (HfOx)-based memristor is used to achieve PUF concealment/recovery with SET/RESET operations efficiently. PUF recovery with a zero-bit error rate and remarkable attack resistance are achieved simultaneously with negligible circuit overhead. This concealable PUF provides a promising opportunity to build memristive hardware systems with effective security in the near future.

Memristor-based analogue computing for brain-inspired sound localization with in situ training.

The human nervous system senses the physical world in an analogue but efficient way. As a crucial ability of the human brain, sound localization is a representative analogue computing task and often employed in virtual auditory systems. Different from well-demonstrated classification applications, all output neurons in localization tasks contribute to the predicted direction, introducing much higher challenges for hardware demonstration with memristor arrays. In this work, with the proposed multi-threshold-update scheme, we experimentally demonstrate the in-situ learning ability of the sound localization function in a 1K analogue memristor array. The experimental and evaluation results reveal that the scheme improves the training accuracy by ∼45.7% compared to the existing method and reduces the energy consumption by ∼184× relative to the previous work. This work represents a significant advance towards memristor-based auditory localization system with low energy consumption and high performance.

Rotating neurons for all-analog implementation of cyclic reservoir computing.

Hardware implementation in resource-efficient reservoir computing is of great interest for neuromorphic engineering. Recently, various devices have been explored to implement hardware-based reservoirs. However, most studies were mainly focused on the reservoir layer, whereas an end-to-end reservoir architecture has yet to be developed. Here, we propose a versatile method for implementing cyclic reservoirs using rotating elements integrated with signal-driven dynamic neurons, whose equivalence to standard cyclic reservoir algorithm is mathematically proven. Simulations show that the rotating neuron reservoir achieves record-low errors in a nonlinear system approximation benchmark. Furthermore, a hardware prototype was developed for near-sensor computing, chaotic time-series prediction and handwriting classification. By integrating a memristor array as a fully-connected output layer, the all-analog reservoir computing system achieves 94.0% accuracy, while simulation shows >1000× lower system-level power than prior works. Therefore, our work demonstrates an elegant rotation-based architecture that explores hardware physics as computational resources for high-performance reservoir computing.

Adaptive optimal output regulation for wheel-legged robot Ollie: A data-driven approach.

The dynamics of a robot may vary during operation due to both internal and external factors, such as non-ideal motor characteristics and unmodeled loads, which would lead to control performance deterioration and even instability. In this paper, the adaptive optimal output regulation (AOOR)-based controller is designed for the wheel-legged robot Ollie to deal with the possible model uncertainties and disturbances in a data-driven approach. We test the AOOR-based controller by forcing the robot to stand still, which is a conventional index to judge the balance controller for two-wheel robots. By online training with small data, the resultant AOOR achieves the optimality of the control performance and stabilizes the robot within a small displacement in rich experiments with different working conditions. Finally, the robot further balances a rolling cylindrical bottle on its top with the balance control using the AOOR, but it fails with the initial controller. Experimental results demonstrate that the AOOR-based controller shows the effectiveness and high robustness with model uncertainties and external disturbances.

Monolayer MoS2 Synaptic Transistors for High-Temperature Neuromorphic Applications.

As essential units in an artificial neural network (ANN), artificial synapses have to adapt to various environments. In particular, the development of synaptic transistors that can work above 125 °C is desirable. However, it is challenging due to the failure of materials or mechanisms at high temperatures. Here, we report a synaptic transistor working at hundreds of degrees Celsius. It employs monolayer MoS2 as the channel and Na+-diffused SiO2 as the ionic gate medium. A large on/off ratio of 106 can be achieved at 350 °C, 5 orders of magnitude higher than that of a normal MoS2 transistor in the same range of gate voltage. The short-term plasticity has a synaptic transistor function as an excellent low-pass dynamic filter. Long-term potentiation/depression and spike-timing-dependent plasticity are demonstrated at 150 °C. An ANN can be simulated, with the recognition accuracy reaching 90%. Our work provides promising strategies for high-temperature neuromorphic applications.

Analog memristive synapse based on topotactic phase transition for high-performance neuromorphic computing and neural network pruning.

Inspired by the human brain, nonvolatile memories (NVMs)-based neuromorphic computing emerges as a promising paradigm to build power-efficient computing hardware for artificial intelligence. However, existing NVMs still suffer from physically imperfect device characteristics. In this work, a topotactic phase transition random-access memory (TPT-RAM) with a unique diffusive nonvolatile dual mode based on SrCoO x is demonstrated. The reversible phase transition of SrCoO x is well controlled by oxygen ion migrations along the highly ordered oxygen vacancy channels, enabling reproducible analog switching characteristics with reduced variability. Combining density functional theory and kinetic Monte Carlo simulations, the orientation-dependent switching mechanism of TPT-RAM is investigated synergistically. Furthermore, the dual-mode TPT-RAM is used to mimic the selective stabilization of developing synapses and implement neural network pruning, reducing ~84.2% of redundant synapses while improving the image classification accuracy to 99%. Our work points out a new direction to design bioplausible memristive synapses for neuromorphic computing.

Dynamic memristor-based reservoir computing for high-efficiency temporal signal processing.

Reservoir computing is a highly efficient network for processing temporal signals due to its low training cost compared to standard recurrent neural networks, and generating rich reservoir states is critical in the hardware implementation. In this work, we report a parallel dynamic memristor-based reservoir computing system by applying a controllable mask process, in which the critical parameters, including state richness, feedback strength and input scaling, can be tuned by changing the mask length and the range of input signal. Our system achieves a low word error rate of 0.4% in the spoken-digit recognition and low normalized root mean square error of 0.046 in the time-series prediction of the Hénon map, which outperforms most existing hardware-based reservoir computing systems and also software-based one in the Hénon map prediction task. Our work could pave the road towards high-efficiency memristor-based reservoir computing systems to handle more complex temporal tasks in the future.

High-Uniformity Threshold Switching HfO2-Based Selectors with Patterned Ag Nanodots.

High-performance selector devices are essential for emerging nonvolatile memories to implement high-density memory storage and large-scale neuromorphic computing. Device uniformity is one of the key challenges which limit the practical applications of threshold switching selectors. Here, high-uniformity threshold switching HfO2-based selectors are fabricated by using e-beam lithography to pattern controllable Ag nanodots (NDs) with high order and uniform size in the cross-point region. The selectors exhibit excellent bidirectional threshold switching performance, including low leakage current (<1 pA), high on/off ratio (>108), high endurance (>108 cycles), and fast switching speed (≈75 ns). The patterned Ag NDs in the selector help control the number of Ag atoms diffusing into HfO2 and confine the positions to form reproducible filaments. According to the statistical analysis, the Ag NDs selectors show much smaller cycle-to-cycle and device-to-device variations (C V < 10%) compared to control samples with nonpatterned Ag thin film. Furthermore, when integrating the Ag NDs selector with resistive switching memory in one-selector-one-resistor (1S1R) structure, the reduced selector variation helps significantly reduce the bit error rate in 1S1R crossbar array. The high-uniformity Ag NDs selectors offer great potential in the fabrication of large-scale 1S1R crossbar arrays for future memory and neuromorphic computing applications.

Multichannel parallel processing of neural signals in memristor arrays.

Fully implantable neural interfaces with massive recording channels bring the gospel to patients with motor or speech function loss. As the number of recording channels rapidly increases, conventional complementary metal-oxide semiconductor (CMOS) chips for neural signal processing face severe challenges on parallelism scalability, computational cost, and power consumption. In this work, we propose a previously unexplored approach for parallel processing of multichannel neural signals in memristor arrays, taking advantage of their rich dynamic characteristics. The critical information of neural signal waveform is extracted and encoded in the memristor conductance modulation. A signal segmentation scheme is developed to adapt to device variations. To verify the fidelity of the processed results, seizure prediction is further demonstrated, with high accuracy above 95% and also more than 1000× improvement in power efficiency compared with CMOS counterparts. This work suggests that memristor arrays could be a promising multichannel signal processing module for future implantable neural interfaces.

Neural signal analysis with memristor arrays towards high-efficiency brain-machine interfaces.

Brain-machine interfaces are promising tools to restore lost motor functions and probe brain functional mechanisms. As the number of recording electrodes has been exponentially rising, the signal processing capability of brain-machine interfaces is falling behind. One of the key bottlenecks is that they adopt conventional von Neumann architecture with digital computation that is fundamentally different from the working principle of human brain. In this work, we present a memristor-based neural signal analysis system, where the bio-plausible characteristics of memristors are utilized to analyze signals in the analog domain with high efficiency. As a proof-of-concept demonstration, memristor arrays are used to implement the filtering and identification of epilepsy-related neural signals, achieving a high accuracy of 93.46%. Remarkably, our memristor-based system shows nearly 400× improvements in the power efficiency compared to state-of-the-art complementary metal-oxide-semiconductor systems. This work demonstrates the feasibility of using memristors for high-performance neural signal analysis in next-generation brain-machine interfaces.