Retinotopic organization of early visual spatial attention effects as revealed by PET and ERPs.

Cerebral blood flow PET scans and high-density event-related potentials (ERPs) were recorded (separate sessions) while subjects viewed rapidly-presented, lower-visual-field, bilateral stimuli. Active attention to a designated side of the stimuli (relative to passive-viewing conditions) resulted in an enhanced ERP positivity (P1 effect) from 80-150 msec over occipital scalp areas contralateral to the direction of attention. In PET scans, active attention vs. passive showed strong activation in the contralateral dorsal occipital cortex, thus following the retinotopic organization of the early extrastriate visual sensory areas, with some weaker activation in the contralateral fusiform. Dipole modeling seeded by the dorsal occipital PET foci yielded an excellent fit for the P1 attention effect. In contrast, dipoles constrained to the fusiform foci fit the P1 effect poorly, and, when the location constraints were released, moved upward to the dorsal occipital locations during iterative dipole fitting. These results argue that the early ERP P1 attention effects for lower-visual-field stimuli arise mainly from these dorsal occipital areas and thus also follow the retinotopic organization of the visual sensory input pathways. These combined PET/ERP data therefore provide strong evidence that sustained visual spatial attention results in a preset, top-down biasing of the early sensory input channels in a retinotopically organized way.

FPGA implementation of VXIbus interface hardware.

The HP E1399A development card is a B-size, register based device that can be used to simplify the development of simple, custom VXIbus instruments. The E1399A provides interface logic that buffers a 16-bit bidirectional data bus and performs other functions required by the VXIbus standard. However, the amount of interface logic required is high enough to substantially reduce the breadboard area that is available to the user. This paper reports on evaluation of field programmable gate array (FPGA) technology to the implementation of the VXIbus interface circuitry. Using FPGAs (Xilinx), all the logic of the E1399A can be fit into at most two low cost gate array packages with an attendant savings in board space. This results in a reliable design that provides the interface between the VXIbus and the user's custom circuitry.