Quantitative three-dimensional carrier mapping in nanowire-based transistors using scanning spreading resistance microscopy.

The performance of nanoelectronic devices critically depends on the distribution of charge carriers inside such structures. High-vacuum scanning spreading resistance microscopy (HV-SSRM) has established as the method of choice for quantitative 2D-carrier mapping in nanoscale devices during the last decade. However, due to the 3D-nature of these nanoscale device architectures, dopant incorporation and dopant diffusion mechanisms can vary for any of the three dimensions, depending on the particular processes used. Therefore, mapping of carriers in three dimensions with high spatial resolution is inevitable to study and understand the distribution of active dopants in confined 3D-volumes and ultimately to support the process development of next generation devices. In this work, we present for the first time an approach to extend the capabilities of SSRM from an inherent 2D-carrier profiling technique towards a quantitative 3D-characterization technique based on the example of a nanowire (NW)-based heterojunction (SiGe-Si) tunneling transistor. In order to implement a 3D-methodology with a 2D-imaging technique, we acquired 2D-carrier concentration maps on successive cross-section planes through the device of interest. This was facilitated by arranging several devices in a staggered array, allowing to produce a series of cross-sections with incremental offset by a single cleave. A dedicated interpolation algorithm especially suited for structures with rotational symmetry like NWs was developed in order to reconstruct a 3D-carrier distribution map. The validity of the method was assessed by proving the absence of variations in carrier distribution in the third dimension, as expected for NWs etched into a blanket stack.

Observation of diameter dependent carrier distribution in nanowire-based transistors.

The successful implementation of nanowire (NW) based field-effect transistors (FET) critically depends on quantitative information about the carrier distribution inside such devices. Therefore, we have developed a method based on high-vacuum scanning spreading resistance microscopy (HV-SSRM) which allows two-dimensional (2D) quantitative carrier profiling of fully integrated silicon NW-based tunnel-FETs (TFETs) with 2 nm spatial resolution. The key elements of our characterization procedure are optimized NW cleaving and polishing steps, the use of in-house fabricated ultra-sharp diamond tips, measurements in high vacuum and a dedicated quantification procedure accounting for the Schottky-like tip-sample contact affected by surface states. In the case of the implanted TFET source regions we find a strong NW diameter dependence of conformality, junction abruptness and gate overlap, quantitatively in agreement with process simulations. In contrast, the arsenic doped drain regions reveal an unexpected NW diameter dependent dopant deactivation. The observed lower drain doping for smaller diameters is reflected in the device characteristics by lower TFET off-currents, as measured experimentally and confirmed by device simulations.

Optimization of multi-walled carbon nanotube-metal contacts by electrical stressing.

We present experimental data on the contact resistances of three different metal probes, tungsten, palladium and indium, with chemical vapour deposited (CVD) multi-wall carbon nanotubes (MWCNTs). We demonstrate that there is an irreversible modification of the contacts following electrical stressing whereby the circuit resistance converges towards its optimal value prior to current-induced tube failure. Once the probe-MWCNT contact is broken, subsequent recontact experiments reveal that the circuit resistance returns to its initial high level, demonstrating that the modification occurs at the probe contact location and not elsewhere in the circuit. Contact studies with the different metals reveal that Pd metal provides the lowest resistance contact to the MWCNT in our sample.