All van der Waals Semiconducting PtSe2 Field Effect Transistors with Low Contact Resistance Graphite Electrodes.

Contact resistance is a multifaceted challenge faced by the 2D materials community. Large Schottky barrier heights and gap-state pinning are active obstacles that require an integrated approach to achieve the development of high-performance electronic devices based on 2D materials. In this work, we present semiconducting PtSe2 field effect transistors with all-van-der-Waals electrode and dielectric interfaces. We use graphite contacts, which enable high ION/IOFF ratios up to 109 with currents above 100 µA µm-1 and mobilities of 50 cm2 V-1 s-1 at room temperature and over 400 cm2 V-1 s-1 at 10 K. The devices exhibit high stability with a maximum hysteresis width below 36 mV nm-1. The contact resistance at the graphite-PtSe2 interface is found to be below 700 Ω µm. Our results present PtSe2 as a promising candidate for the realization of high-performance 2D circuits built solely with 2D materials.

Over- and Undercoordinated Atoms as a Source of Electron and Hole Traps in Amorphous Silicon Nitride (a-Si3N4).

Silicon nitride films are widely used as the charge storage layer of charge trap flash (CTF) devices due to their high charge trap densities. The nature of the charge trapping sites in these materials responsible for the memory effect in CTF devices is still unclear. Most prominently, the Si dangling bond or K-center has been identified as an amphoteric trap center. Nevertheless, experiments have shown that these dangling bonds only make up a small portion of the total density of electrical active defects, motivating the search for other charge trapping sites. Here, we use a machine-learned force field to create model structures of amorphous Si3N4 by simulating a melt-and-quench procedure with a molecular dynamics algorithm. Subsequently, we employ density functional theory in conjunction with a hybrid functional to investigate the structural properties and electronic states of our model structures. We show that electrons and holes can localize near over- and under-coordinated atoms, thereby introducing defect states in the band gap after structural relaxation. We analyze these trapping sites within a nonradiative multi-phonon model by calculating relaxation energies and thermodynamic charge transition levels. The resulting defect parameters are used to model the potential energy curves of the defect systems in different charge states and to extract the classical energy barrier for charge transfer. The high energy barriers for charge emission compared to the vanishing barriers for charge capture at the defect sites show that intrinsic electron traps can contribute to the memory effect in charge trap flash devices.

Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning.

Electronic devices based on two-dimensional semiconductors suffer from limited electrical stability because charge carriers originating from the semiconductors interact with defects in the surrounding insulators. In field-effect transistors, the resulting trapped charges can lead to large hysteresis and device drifts, particularly when common amorphous gate oxides (such as silicon or hafnium dioxide) are used, hindering stable circuit operation. Here, we show that device stability in graphene-based field-effect transistors with amorphous gate oxides can be improved by Fermi-level tuning. We deliberately tune the Fermi level of the channel to maximize the energy distance between the charge carriers in the channel and the defect bands in the amorphous aluminium gate oxide. Charge trapping is highly sensitive to the energetic alignment of the Fermi level of the channel with the defect band in the insulator, and thus, our approach minimizes the amount of electrically active border traps without the need to reduce the total number of traps in the insulator.

Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. Also, small circuits consisting of a few transistors have been demonstrated, including inverters, ring oscillators, and static random access memory cells. However, for industrial applications, both time-zero and time-dependent variability in the performance of the transistors appear critical. While time-zero variability is primarily related to immature processing, time-dependent drifts are dominated by charge trapping at defects located at the channel/insulator interface and in the insulator itself, which can substantially degrade the stability of circuits. At the current state of the art, 2D transistors typically exhibit a few orders of magnitude higher trap densities than silicon devices, which considerably increases their time-dependent variability, resulting in stability and yield issues. Here, the stability of currently available 2D electronics is carefully evaluated using circuit simulations to determine the impact of transistor-related issues on the overall circuit performance. The results suggest that while the performance parameters of transistors based on certain material combinations are already getting close to being competitive with Si technologies, a reduction in variability and defect densities is required. Overall, the criteria for parameter variability serve as guidance for evaluating the future development of 2D technologies.

Reliability of Miniaturized Transistors from the Perspective of Single-Defects.

To analyze the reliability of semiconductor transistors, changes in the performance of the devices during operation are evaluated. A prominent effect altering the device behavior are the so called bias temperature instabilities (BTI), which emerge as a drift of the device threshold voltage over time. With ongoing miniaturization of the transistors towards a few tens of nanometer small devices the drift of the threshold voltage is observed to proceed in discrete steps. Quite interestingly, each of these steps correspond to charge capture or charge emission event of a certain defect in the atomic structure of the device. This observation paves the way for studying device reliability issues like BTI at the single-defect level. By considering single-defects the physical mechanism of charge trapping can be investigated very detailed. An in-depth understanding of the intricate charge trapping kinetics of the defects is essential for modeling of the device behavior and also for accurate estimation of the device lifetime amongst others. In this article the recent advancements in characterization, analysis and modeling of single-defects are reviewed.

Semi-Automated Extraction of the Distribution of Single Defects for nMOS Transistors.

Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is typically beneficial for their operating characteristics, such as switching speed and power consumption, but at the same time miniaturization also leads to increased variability among nominally identical devices. Adverse effects due to oxide traps in particular become a serious issue for device performance and reliability. While the average number of defects per device is lower for scaled devices, the impact of the oxide defects is significantly more pronounced than in large area transistors. This combination enables the investigation of charge transitions of single defects. In this study, we perform random telegraph noise (RTN) measurements on about 300 devices to statistically characterize oxide defects in a Si/SiO 2 technology. To extract the noise parameters from the measurements, we make use of the Canny edge detector. From the data, we obtain distributions of the step heights of defects, i.e., their impact on the threshold voltage of the devices. Detailed measurements of a subset of the defects further allow us to extract their vertical position in the oxide and their trap level using both analytical estimations and full numerical simulations. Contrary to published literature data, we observe a bimodal distribution of step heights, while the extracted distribution of trap levels agrees well with recent studies.

Characterization of Single Defects in Ultrascaled MoS2 Field-Effect Transistors.

MoS2 has received a lot of attention lately as a semiconducting channel material for electronic devices, in part due to its large band gap as compared to that of other 2D materials. Yet, the performance and reliability of these devices are still severely limited by defects which act as traps for charge carriers, causing severely reduced mobilities, hysteresis, and long-term drift. Despite their importance, these defects are only poorly understood. One fundamental problem in defect characterization is that due to the large defect concentration only the average response to bias changes can be measured. On the basis of such averaged data, a detailed analysis of their properties and identification of particular defect types are difficult. To overcome this limitation, we here characterize single defects on MoS2 devices by performing measurements on ultrascaled transistors (∼65 × 50 nm) which contain only a few defects. These single defects are characterized electrically at varying gate biases and temperatures. The measured currents contain random telegraph noise, which is due to the transfer of charge between the channel of the transistors and individual defects, visible only due to the large impact of a single elementary charge on the local electrostatics in these small devices. Using hidden Markov models for statistical analysis, we extract the charge capture and emission times of a number of defects. By comparing the bias-dependence of the measured capture and emission times to the prediction of theoretical models, we provide simple rules to distinguish oxide traps from adsorbates on these back-gated devices. In addition, we give simple expressions to estimate the vertical and energetic positions of the defects. Using the methods presented in this work, it is possible to locate the sources of performance and reliability limitations in 2D devices and to probe defect distributions in oxide materials with 2D channel materials.

Long-Term Stability and Reliability of Black Phosphorus Field-Effect Transistors.

Black phosphorus has been recently suggested as a very promising material for use in 2D field-effect transistors. However, due to its poor stability under ambient conditions, this material has not yet received as much attention as for instance MoS2. We show that the recently demonstrated Al2O3 encapsulation leads to highly stable devices. In particular, we report our long-term study on highly stable black phosphorus field-effect transistors, which show stable device characteristics for at least eight months. This high stability allows us to perform a detailed analysis of their reliability with respect to hysteresis as well as the arguably most important reliability issue in silicon technologies, the bias-temperature instability. We find that the hysteresis in these transistors depends strongly on the sweep rate and temperature. Moreover, the hysteresis dynamics in our devices are reproducible over a long time, which underlines their high reliability. Also, by using detailed physical models for oxide traps developed for Si technologies, we are able to capture the channel electrostatics of the black phosphorus FETs and determine the position of the defect energy band. Finally, we demonstrate that both hysteresis and bias-temperature instabilities are due to thermally activated charge trapping/detrapping by oxide traps and can be reduced if the device is covered by Teflon-AF.