Room-Temperature Growth of Square-Millimeter Single-Crystalline Two-Dimensional Metal Halides on Silicon.

Silicon is the cornerstone of electronics and photonics. In this context, almost all integrated devices derived from two-dimensional (2D) materials stay rooted in silicon technology. However, as the growth substrate, silicon has long been thought to be a hindrance for growing 2D materials through bottom-up methods that require high growth temperatures, and thus, indirect routes are usually considered instead. Although promising growth of large-area 2D materials on silicon has been demonstrated, the direct growth of single-crystalline materials using low-thermal-budget synthesis methods remains challenging. Here, we report the room-temperature growth of millimeter-scale single-crystal 2D metal halides on silicon substrates with a hydroxyl-terminated surface. Theoretical calculations reveal that the activation energy for surface diffusion can be reduced by an order of magnitude by terminating the surface with hydroxyl groups, from which on-silicon growth is greatly facilitated at room temperature and enables a 4-order-of-magnitude increase in area. The high quality and uniformity of the resulting single crystals are further evidenced. The optoelectronic devices employing the as-grown materials show an ultralow dark current of 10-13 A and a high detectivity of 1013 Jones, thereby corroborating a weak-light detection ability. These results would point to a rich space of surface modulation that can be used to surmount current limitations and demonstrate a promising strategy for growing 2D materials directly on silicon at room temperature to produce large single crystals.

Deep-trap dominated degradation of the endurance characteristics in OFET memory with polymer charge-trapping layer.

Organic field-effect transistors (OFETs) with polymer charge-trapping dielectric, which exhibit many advantages over Si-based memory devices such as low cost, light weight, and flexibility, still suffer challenges in practical application due to the unsatisfied endurance characteristics and even the lack of fundamental of behind mechanism. Here, we revealed that the degradation of endurance characteristics of pentacene OFET with poly(2-vinyl naphthalene) (PVN) as charge-storage layer is dominated by the deep hole-traps in PVN by using the photo-stimulated charge de-trapping technique with the fiber-coupled monochromatic-light probes. The depth distribution of hole-traps in PVN film of pentacene OFET is also provided.

Enhancement of Memory Properties of Pentacene Field-Effect Transistor by the Reconstruction of an Inner Vertical Electric Field with an n-Type Semiconductor Interlayer.

Organic field-effect transistors (OFETs) as nonvolatile memory units are essential for lightweight and flexible electronics, yet the practical application remains a great challenge. The positively charged defects in pentacene film at the interface between pentacene and polymer caused by environmental conditions, as revealed by theoretical and experimental research works, result in unacceptable high programming/erasing (P/E) gate voltages in pentacene OFETs with polymer charge-trapping dielectric. Here, we report a pentacene OFET in which an n-type semiconductor layer was intercalated between a polymer and a blocking insulator. In this structure, the hole barrier caused by the defect layer can be adjusted by the thickness and charge-carrier density of the n-type semiconductor interlayer based on the electrostatic induction theory. This idea was implemented in an OFET structure Cu/pentacene/poly(2-vinyl naphthalene) (PVN)/ZnO/SiO2/Si(p+), which shows low P/E gate voltages, large field-effect mobility (0.73 cm2 V-1 s-1), fast P/E speeds (responding to a pulse width of 5 × 10-4 s), and long retention time in air.