Analysis of Variation and Ferroelectric Layer Thickness on Negative Capacitance Nanowire Field-Effect Transistor.

We investigate the interrelation between some variations and the stability of Negative Capacitance Field-Effect Transistors (NC FETs). When a variation effect is considered, stability issues which are making hysteretic operation should be considered for NC FETs as well. In this paper, to make sure of stability and hysteresis-free operation, a thickness margin of ferroelectric layer is suggested. It is the easiest solution for designing and surest method of vouching for hysteresis-free operation. Although some disadvantages which make subthreshold swing (SS) a bit higher than without a margin on thickness of ferroelectric layer (TFE) can be caused, both still high performance and stable operation can be achieved.

Effect of Various Geometry Parameters on the Performance of Nanoplate Field Effect Transistor with Negative Capacitance.

In this paper, we investigate the impact of geometry parameters such as ferroelectric layer thickness (TFE), extension length (LExt), overlap length (Lov) on negative capacitance FET (NCFET). The NCFET is designed using HfZrO2 (HZO) ferroelectric materials and the Nanoplate FET (NPFET) presented as a next generation device. We use the 3-D TCAD Sentaurus simulator to analyze characteristics of the NCFET. The NCFET designed considering the stable condition overcomes the Boltzmann limit (i.e., the physical limit in the S.S., which is 60 mV/decade at 300 K) through the steep subthreshold swing (S.S.) and exhibits negative Drain-induced barrier lowering (DIBL) phenomenon. When examining the characteristics of NPFET and NCFET according to LExt and Lov, the NCFET exhibits gate capacitance (Cgg) tendency opposite to that of the NPFET. The NCFET with the scaled VDD has a significant advantage over the gate delay (τd). The NCFET has better performance in environments where conventional device is more vulnerable to short channel effects (SCEs).