The Reflectance Characteristics of an Inverse Moth-Eye Structure in a Silicon Substrate Depending on SF6/O2 Plasma Etching Conditions.

The global RE100 campaign is attracting attention worldwide due to climate change caused by global warming, increasingly highlighting the efficiency of renewable energy. Texturing of photovoltaic devices increases the devices' efficiency by reducing light reflectance at their surfaces. This study introduces the change in light reflectance following the process conditions of plasma etching as a texturing process to increase the efficiency of photovoltaic cells. Isotropic etching was induced through plasma using SF6 gas, and the etch profile was modulated by adding O2 gas to reduce light reflectance. A high etch rate produces high surface roughness, which results in low surface reflectance properties. The inverse moth-eye structure was implemented using a square PR pattern arranged diagonally and showed the minimum reflectance in visible light at a tip spacing of 1 µm. This study can be applied to the development of higher-efficiency optical devices.

Sub-30 nm gate template fabrication for nanoimprint lithography using spacer patterning technology.

In this study, we present a spacer patterning technology for sub-30 nm gate template which is used for nano-scale MOSFETs fabrication. A spacer patterning technology using a poly-silicon micro-feature and a chemical vapor deposition (CVD) SiO2 spacer has been developed, and the sub-30 nm structures by conventional dry etching and chemical mechanical polishing are demonstrated. The minimum-sized features are defined not by the photolithography but by the CVD film thickness. Therefore, this technology yields a large-area template with critical dimension of minimum-sized features much smaller than that achieved by optical lithography.