Stabilizing amplifier with a programmable load line for characterization of nanodevices with negative differential resistance.

Resistive switching devices and other components with negative differential resistance (NDR) are emerging as possible electronic constituents of next-generation computing architectures. Due to the exhibited NDR effects, switching operations are strongly affected by the presence of resistance in series with the memory cell. Experimental measurements useful in the development of these devices use a deliberate addition of series resistance, which can be done either by integrating resistors on-chip or by connecting external components to the wafer probing system. The former approach is considered inflexible because the resistance value attached to a given device cannot be changed or removed, while the latter approach tends to create parasitic effects that impact controllability and interfere with measurements. In this work, we introduce a circuit design for flexible characterization of two-terminal nanodevices that provides a programmatically adjustable external series resistance while maintaining low parasitic capacitance. Experimental demonstrations show the impact of the series resistance on NDR and resistive switching measurements.

Current-limiting amplifier for high speed measurement of resistive switching data.

Resistive switching devices, important for emerging memory and neuromorphic applications, face significant challenges related to the control of delicate filamentary states in the oxide material. As a device switches, its rapid conductivity change is involved in a positive feedback process that would lead to runaway destruction of the cell without current, voltage, or energy limitation. Typically, cells are directly patterned on MOS transistors to limit the current, but this approach is very restrictive as the necessary integration limits the materials available as well as the fabrication cycle time. In this article, we propose an external circuit to cycle resistive memory cells, capturing the full transfer curves while driving the cells in a way that suppresses runaway transitions. Using this circuit, we demonstrate the acquisition of 105 I, V loops per second without using on-wafer current limiting transistors. This setup brings voltage sweeping measurements to a relevant timescale for applications and enables many new experimental possibilities for device evaluation in a statistical context.