An Event-Driven Approach to Genotype Imputation on a Custom RISC-V Cluster.

This article proposes an event-driven solution to genotype imputation, a technique used to statistically infer missing genetic markers in DNA. The work implements the widely accepted Li and Stephens model, primary contributor to the computational complexity of modern x86 solutions, in an attempt to determine whether further investigation of the application is warranted in the event-driven domain. The model is implemented using graph-based Hidden Markov Modeling and executed as a customized forward/backward dynamic programming algorithm. The solution uses an event-driven paradigm to map the algorithm to thousands of concurrent cores, where events are small messages that carry both control and data within the algorithm. The design of a single processing element is discussed. This is then extended across multiple cores and executed on a custom RISC-V NoC cluster called POETS. Results demonstrate how the algorithm scales over increasing hardware resources and a multi-core run demonstrates a 270X reduction in wall-clock processing time when compared to a single-threaded x86 solution. Optimisation of the algorithm via linear interpolation is then introduced and tested, with results demonstrating a wall-clock reduction time of  âˆ¼ 5 orders of magnitude when compared to a similarly optimised x86 solution.

Time derivatives via interconnected waveguides.

Electromagnetic wave-based analogue computing has become an interesting computing paradigm demonstrating the potential for high-throughput, low power, and parallel operations. In this work, we propose a technique for the calculation of derivatives of temporal signals by exploiting transmission line techniques. We consider multiple interconnected waveguides (with some of them being closed-ended stubs) forming junctions. The transmission coefficient of the proposed structure is then tailored by controlling the length and number of stubs at the junction, such that the differentiation operation is applied directly onto the envelope of an incident signal sinusoidally modulated in the time domain. The physics behind the proposed structure is explained in detail and a full theoretical description of this operation is presented, demonstrating how this technique can be used to calculate higher order or even fractional temporal derivatives. We envision that these results may enable the development of further time domain wave-based analogue processors by exploiting waveguide junctions, opening new opportunities for wave-based single operators and systems.

REDRESS: Generating Compressed Models for Edge Inference Using Tsetlin Machines.

Inference at-the-edge using embedded machine learning models is associated with challenging trade-offs between resource metrics, such as energy and memory footprint, and the performance metrics, such as computation time and accuracy. In this work, we go beyond the conventional Neural Network based approaches to explore Tsetlin Machine (TM), an emerging machine learning algorithm, that uses learning automata to create propositional logic for classification. We use algorithm-hardware co-design to propose a novel methodology for training and inference of TM. The methodology, called REDRESS, comprises independent TM training and inference techniques to reduce the memory footprint of the resulting automata to target low and ultra-low power applications. The array of Tsetlin Automata (TA) holds learned information in the binary form as bits: {0,1}, called excludes and includes, respectively. REDRESS proposes a lossless TA compression method, called the include-encoding, that stores only the information associated with includes to achieve over 99% compression. This is enabled by a novel computationally minimal training procedure, called the Tsetlin Automata Re-profiling, to improve the accuracy and increase the sparsity of TA to reduce the number of includes, hence, the memory footprint. Finally, REDRESS includes an inherently bit-parallel inference algorithm that operates on the optimally trained TA in the compressed domain, that does not require decompression during runtime, to obtain high speedups when compared with the state-of-the-art Binary Neural Network (BNN) models. In this work, we demonstrate that using REDRESS approach, TM outperforms BNN models on all design metrics for five benchmark datasets viz. MNIST, CIFAR2, KWS6, Fashion-MNIST and Kuzushiji-MNIST. When implemented on an STM32F746G-DISCO microcontroller, REDRESS obtained speedups and energy savings ranging 5-5700× compared with different BNN models.

CORAL: Verification-Aware OpenCL Based Read Mapper for Heterogeneous Systems.

Genomics has the potential to transform medicine from reactive to a personalized, predictive, preventive, and participatory (P4) form. Being a Big Data application with continuously increasing rate of data production, the computational costs of genomics have become a daunting challenge. Most modern computing systems are heterogeneous consisting of various combinations of computing resources, such as CPUs, GPUs, and FPGAs. They require platform-specific software and languages to program making their simultaneous operation challenging. Existing read mappers and analysis tools in the whole genome sequencing (WGS) pipeline do not scale for such heterogeneity. Additionally, the computational cost of mapping reads is high due to expensive dynamic programming based verification, where optimized implementations are already available. Thus, improvement in filtration techniques is needed to reduce verification overhead. To address the aforementioned limitations with regards to the mapping element of the WGS pipeline, we propose a Cross-platfOrm Read mApper using opencL (CORAL). CORAL is capable of executing on heterogeneous devices/platforms, simultaneously. It can reduce computational time by suitably distributing the workload without any additional programming effort. We showcase this on a quadcore Intel CPU along with two Nvidia GTX 590 GPUs, distributing the workload judiciously to achieve up to 2× speedup compared to when, only, the CPUs are used. To reduce the verification overhead, CORAL dynamically adapts k-mer length during filtration. We demonstrate competitive timings in comparison with other mappers using real and simulated reads. CORAL is available at: https://github.com/nclaes/CORAL.

Learning automata based energy-efficient AI hardware design for IoT applications.

Energy efficiency continues to be the core design challenge for artificial intelligence (AI) hardware designers. In this paper, we propose a new AI hardware architecture targeting Internet of Things applications. The architecture is founded on the principle of learning automata, defined using propositional logic. The logic-based underpinning enables low-energy footprints as well as high learning accuracy during training and inference, which are crucial requirements for efficient AI with long operating life. We present the first insights into this new architecture in the form of a custom-designed integrated circuit for pervasive applications. Fundamental to this circuit is systematic encoding of binarized input data fed into maximally parallel logic blocks. The allocation of these blocks is optimized through a design exploration and automation flow using field programmable gate array-based fast prototypes and software simulations. The design flow allows for an expedited hyperparameter search for meeting the conflicting requirements of energy frugality and high accuracy. Extensive validations on the hardware implementation of the new architecture using single- and multi-class machine learning datasets show potential for significantly lower energy than the existing AI hardware architectures. In addition, we demonstrate test accuracy and robustness matching the software implementation, outperforming other state-of-the-art machine learning algorithms. This article is part of the theme issue 'Advanced electromagnetic non-destructive evaluation and smart monitoring'.

Neural network design for energy-autonomous artificial intelligence applications using temporal encoding.

Neural networks (NNs) are steering a new generation of artificial intelligence (AI) applications at the micro-edge. Examples include wireless sensors, wearables and cybernetic systems that collect data and process them to support real-world decisions and controls. For energy autonomy, these applications are typically powered by energy harvesters. As harvesters and other power sources which provide energy autonomy inevitably have power variations, the circuits need to robustly operate over a dynamic power envelope. In other words, the NN hardware needs to be able to function correctly under unpredictable and variable supply voltages. In this paper, we propose a novel NN design approach using the principle of pulse width modulation (PWM). PWM signals represent information with their duty cycle values which may be made independent of the voltages and frequencies of the carrier signals. We design a PWM-based perceptron which can serve as the fundamental building block for NNs, by using an entirely new method of realizing arithmetic in the PWM domain. We analyse the proposed approach building from a 3 × 3 perceptron circuit to a complex multi-layer NN. Using handwritten character recognition as an exemplar of AI applications, we demonstrate the power elasticity, resilience and efficiency of the proposed NN design in the presence of functional and parametric variations including large voltage variations in the power supply. This article is part of the theme issue 'Harmonizing energy-autonomous computing and intelligence'.

Energy current and computing.

In his seminal Electrical papers, Oliver Heaviside stated 'We reverse this …' referring to the relationship between energy current and state changes in electrical networks. We explore implications of Heaviside's view upon the state changes in electronic circuits, effectively constituting computational processes. Our vision about energy-modulated computing that can be applicable for electronic systems with energy harvesting is introduced. Examples of analysis of computational circuits as loads on power sources are presented. We also draw inspiration from Heaviside's way of using and advancing mathematical methods from the needs of natural physical phenomena. A vivid example of Heavisidian approach to the use of mathematics is in employing series where they emerge out of the spatio-temporal view upon energy flows. Using series expressions, and types of natural discretization in space and time, we explain the processes of discharging a capacitive transmission line, first, through a constant resistor and, second, through a voltage controlled digital circuit. We show that event-based models, such as Petri nets with an explicit notion of causality inherent in them, can be instrumental in creating bridges between electromagnetics and computing.This article is part of the theme issue 'Celebrating 125 years of Oliver Heaviside's 'Electromagnetic Theory''.

Oliver Heaviside's electromagnetic theory.

The year 2018 marks the 125th anniversary of the first of three published volumes on electromagnetic theory by the eminent Victorian electrical engineer, physicist and mathematician, Oliver Heaviside FRS. This commemorative issue of Philosophical Transactions of the Royal Society A celebrates the publication of this work by collecting papers on a broad spectrum across the field of electromagnetic theory, including innovative research papers interspersed between historical perspectives and relevant reviews. Heaviside was a remarkable man, an original thinker with brilliant mathematical powers and physical insight who made many significant contributions in his fields of interest, though he is remembered primarily for his 'step function', commonly used today in many branches of physics, mathematics and engineering. Here, we celebrate the man and his work by illustrating his major contributions and highlighting his great success in solving some of the great telegraphic engineering problems of the Victorian era, in part due to his development and detailed understanding of the governing electromagnetic theory. We celebrate his Electromagnetic theory: three volumes of insights, techniques and understanding from mathematical, physical and engineering perspectives-as dictated by J. C. Maxwell FRS, but interpreted, reformulated and expanded by Heaviside to advance the art and science of electrical engineering beyond all expectations.This article is part of the theme issue 'Celebrating 125 years of Oliver Heaviside's 'Electromagnetic Theory''.

Optogenetics in Silicon: A Neural Processor for Predicting Optically Active Neural Networks.

We present a reconfigurable neural processor for real-time simulation and prediction of opto-neural behaviour. We combined a detailed Hodgkin-Huxley CA3 neuron integrated with a four-state Channelrhodopsin-2 (ChR2) model into reconfigurable silicon hardware. Our architecture consists of a Field Programmable Gated Array (FPGA) with a custom-built computing data-path, a separate data management system and a memory approach based router. Advancements over previous work include the incorporation of short and long-term calcium and light-dependent ion channels in reconfigurable hardware. Also, the developed processor is computationally efficient, requiring only 0.03 ms processing time per sub-frame for a single neuron and 9.7 ms for a fully connected network of 500 neurons with a given FPGA frequency of 56.7 MHz. It can therefore be utilized for exploration of closed loop processing and tuning of biologically realistic optogenetic circuitry.

Towards neuro-silicon interface using reconfigurable dynamic clamping.

Dynamic clamp emerges as an important apparatus to study the intrinsic neuronal properties through close-loop interactions between models and biological neurons. Modelling large-scale neuronal networks in software will result in significant computational delay that becomes a bottleneck to apply dynamic clamp for more complicated systems. In this paper, we present a real-time dynamic clamping system based on field programmable gate arrays (FPGAs) to accelerate the necessary computations. It also provides a flexible platform to reconfigure various model parameters and topologies. Realtime neuronal and synaptic models were implemented in FPGA, and interconnected with the stomatograstric ganglion (STG) nervous system to exemplify the real-time dynamics. Results show that our method can be effectively configured to mimic various biological neural networks and is two orders of magnitude faster than software approach using desktop computer.

Memory efficient on-line streaming for multichannel spike train analysis.

Rapid advances in multichannel neural signal recording technologies in recent years have spawned broad applications in neuro-prostheses and neuro-rehabilitation. The dramatic increase in data bandwidth and volume associated with multichannel recording requires a significant computational effort which presents major design challenges for brain-machine interface (BMI) system in terms of power dissipation and hardware area. In this paper, we present a streaming method for implementing real-time memory efficient neural signal processing hardware. This method exploits the pseudo-stationary property of neural signals and, thus, eliminates the need of temporal storage in batch-based processing. The proposed technique can significantly reduce memory size and dynamic power while effectively maintaining the accuracy of algorithms. The streaming kernel is robust when compared to the batch processing over a range of BMI benchmark algorithms. The advantages of the streaming kernel when implemented on field-programmable gate array (FPGA) devices are also demonstrated.

Is a single cell sensor possible?

A cell-based implant is a miniaturized sensor that can be placed inside a biological living cell. This device would be able to interrogate and possibly affect biological functions in vivo. This paper explores the requirements of such a system; it also investigates the changes that need to be brought about in both fabrication technologies and design methodologies to make this visionary application a reality.