AoCStream: All-on-Chip CNN Accelerator with Stream-Based Line-Buffer Architecture and Accelerator-Aware Pruning.

Convolutional neural networks (CNNs) play a crucial role in many EdgeAI and TinyML applications, but their implementation usually requires external memory, which degrades the feasibility of such resource-hungry environments. To solve this problem, this paper proposes memory-reduction methods at the algorithm and architecture level, implementing a reasonable-performance CNN with the on-chip memory of a practical device. At the algorithm level, accelerator-aware pruning is adopted to reduce the weight memory amount. For activation memory reduction, a stream-based line-buffer architecture is proposed. In the proposed architecture, each layer is implemented by a dedicated block, and the layer blocks operate in a pipelined way. Each block has a line buffer to store a few rows of input data instead of a frame buffer to store the whole feature map, reducing intermediate data-storage size. The experimental results show that the object-detection CNNs of MobileNetV1/V2 and an SSDLite variant, widely used in TinyML applications, can be implemented even on a low-end FPGA without external memory.

Memristive Switching and Density-Functional Theory Calculations in Double Nitride Insulating Layers.

In this paper, we demonstrate a device using a Ni/SiN/BN/p+-Si structure with improved performance in terms of a good ON/OFF ratio, excellent stability, and low power consumption when compared with single-layer Ni/SiN/p+-Si and Ni/BN/p+-Si devices. Its switching mechanism can be explained by trapping and de-trapping via nitride-related vacancies. We also reveal how higher nonlinearity and rectification ratio in a bilayer device is beneficial for enlarging the read margin in a cross-point array structure. In addition, we conduct a theoretical investigation for the interface charge accumulation/depletion in the SiN/BN layers that are responsible for defect creation at the interface and how this accounts for the improved switching characteristics.

Impact of Iterative Deuterium Annealing in Long-Channel MOSFET Performance.

In contrast to conventional forming gas annealing (FGA), high-pressure deuterium annealing (HPD) shows a superior passivation of dangling bonds on the Si/SiO2 interface. However, research detailing the process optimization for HPD has been modest. In this context, this paper demonstrates the iterative impact of HPD for the better fabrication of semiconductor devices. Long-channel gate-enclosed FETs are fabricated as a test vehicle. After each cycle of the annealing, device parameters are extracted and compared depending on the number of the HPD. Based on the results, an HPD condition that maximizes on-state current (ION) but minimizes off-state current (IOFF) can be provided.