Methodology for Testing Key Parameters of Array-Level Small-Area Hafnium-Based Ferroelectric Capacitors Using Time-to-Digital Converter and Capacitance Calibration Circuits.

Hafnium-based ferroelectric memories are a promising approach to enhancing integrated circuit performance, offering advantages such as miniaturization, compatibility with CMOS technology, fast read and write speeds, non-volatility, and low power consumption. However, FeRAM (Ferroelectric Random Access Memory) still faces challenges related to endurance and retention susceptibility to process variations. Hence, testing and obtaining the core parameters of ferroelectric capacitors continuously is essential to investigate these phenomena and explore the potential solution. The traditional method for measuring ferroelectric capacitors has limitations in timing generation capability, introduces parasitic capacitance, and lacks accuracy for small-area capacitors. In this study, we analyzed the working principle of ferroelectric capacitors and designed a method to detect the remnant polarization, saturation polarization, and imprint offset of ferroelectric capacitors. Further, we further proposed a circuit implementation method. The proposed test circuit conquers these limitations and enables high-precision testing of ferroelectric capacitors, contributing to developing hafnium-based ferroelectric memories. The circuit includes a flip-readout circuit, a capacitance calibration circuit, and a voltage-to-time converter and time-to-digital converter (VTC&TDC) readout circuit. According to simulation results, the capacitance calibration circuit reduces the deviation of the capacitance by 84%, and the accuracy of the readout circuit is 5.91 bits, with a readout time of 150 ns and a power consumption of 1 mW. This circuit enables low-cost acquisition of array-level small-area ferroelectric capacitance data, which can guide subsequent device optimization and circuit design.

Temporally gene knockout using heat shock-inducible genome-editing system in plants.

Clustered regularly interspaced short palindromic repeat (CRISPR)/CRISPR-associated nuclease 9 (Cas9) has emerged as a powerful tool to generate targeted loss-of-function mutations for functional genomic studies. As a next step, tools to generate genome modifications in a spatially and temporally precise manner will enable researchers to further dissect gene function. Here, we present two heat shock-inducible genome-editing (IGE) systems that efficiently edit target genes when the system is induced, thus allowing us to target specific developmental stages. For this conditional editing system, we chose the natural heat-inducible promoter from heat-shock protein 18.2 (HSP18.2) from Arabidopsis thaliana and the synthetic heat-inducible promoter heat shock-response element HSE-COR15A to drive the expression of Cas9. We tested these two IGE systems in Arabidopsis using cyclic or continuous heat-shock treatments at the seedling and bolting stages. A real-time quantitative polymerase chain reaction analysis revealed that the HSP18.2 IGE system exhibited higher Cas9 expression levels than the HSE-COR15A IGE system upon both cyclic and continuous treatments. By targeting brassinosteroid-insensitive 1 (BRI1) and phytoene desaturase (PDS), we demonstrate that both cyclic and continuous heat inductions successfully activated the HSP18.2 IGE system at the two developmental stages, resulting in highly efficient targeted mutagenesis and clear phenotypic outcomes. By contrast, the HSE-COR15A IGE system was only induced at the seedling stage and was less effective than the HSP18.2 IGE system in terms of mutagenesis frequencies. The presented heat shock-IGE systems can be conditionally induced to efficiently inactivate genes at any developmental stage and are uniquely suited for the dissection and systematic characterization of essential genes.

Sensing Circuit Design Techniques for RRAM in Advanced CMOS Technology Nodes.

Resistive random access memory (RRAM) is one of the most promising new nonvolatile memories because of its excellent properties. Moreover, due to fast read speed and low work voltage, it is suitable for seldom-write frequent-read applications. However, as technology nodes shrink, RRAM faces many issues, which can significantly degrade RRAM performance. Therefore, it is necessary to optimize the sensing schemes to improve the application range of RRAM. In this paper, the issues faced by RRAM in advanced technology nodes are summarized. Then, the advantages and weaknesses in the novel design and optimization methodologies of sensing schemes are introduced in detail from three aspects, the reference schemes, sensing amplifier schemes, and bit line (BL)-enhancing schemes, according to the development of technology in especially recent years, which can be the reference for designing the sensing schemes. Moreover, the waveforms and results of each method are illustrated to make the design easy to understand. With the development of technology, the sensing schemes of RRAM become higher speed and resolution, low power consumption, and are applied at advanced technology nodes and low working voltage. Now, the most advanced nodes the RRAM applied is 14 nm node, the lowest working voltage can reach 0.32 V, and the shortest access time can be only a few nanoseconds.