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1.
Nanomaterials (Basel) ; 12(21)2022 Oct 28.
Article in English | MEDLINE | ID: mdl-36364596

ABSTRACT

The recent report of a p-type graphene(Gr)/carbon-nanotube(CNT) barristor facilitates the application of graphene barristors in the fabrication of complementary logic devices. Here, a complementary inverter is presented that combines a p-type Gr/CNT barristor with a n-type Gr/MoS2 barristor, and its characteristics are reported. A sub-nW (~0.2 nW) low-power inverter is demonstrated with a moderate gain of 2.5 at an equivalent oxide thickness (EOT) of ~15 nm. Compared to inverters based on field-effect transistors, the sub-nW power consumption was achieved at a much larger EOT, which was attributed to the excellent switching characteristics of Gr barristors.

2.
Nanotechnology ; 32(50)2021 Sep 21.
Article in English | MEDLINE | ID: mdl-34479221

ABSTRACT

We have investigated the effect of an Al2O3passivation layer on the performance of few-layer WS2FETs. While the performance of WS2FETs is often limited by a substantial decrease in carrier mobility owing to charged impurities and a Schottky barrier between the WS2and metal electrodes, the introduction of an Al2O3overlayer by atomic layer deposition (ALD) suppressed the influence of charged impurities by high-κdielectric screening effect and reduced the effective Schottky barrier height. We argue that n-doping of WS2, induced by positive fixed charges formed at Al2O3/WS2interface during the ALD process, is responsible for the reduction of the effective Schottky barrier height in the devices. In addition, the Al2O3passivation layer protected the device from oxidation, and maintained stable electrical performance of the WS2FETs over 57 d. Thus, the ALD of Al2O3overlayer provides a facile method to enhance the performance of WS2FETs and to ensure ambient stability.

3.
ACS Appl Mater Interfaces ; 10(49): 42875-42881, 2018 Dec 12.
Article in English | MEDLINE | ID: mdl-30427172

ABSTRACT

Recently, attempts to overcome the physical limits of memory devices have led to the development of promising materials and architectures for next-generation memory technology. The selector device is one of the essential ingredients of high-density stacked memory systems. However, complicated constituent deposition conditions and thermal degradation are problematic, even with effective selector device materials. Herein, we demonstrate the highly stable and low-threshold voltages of vanadium pentoxide (V2O5) nanosheets synthesized by facile chemical vapor deposition, which have not been previously reported on the threshold switching (TS) properties. The electrons occupying trap sites in poly-crystalline V2O5 nanosheet contribute to the perfectly symmetric TS feature at the bias polarity and low-threshold voltages in V2O5, confirmed by high-resolution transmission electron microscopy measurements. Furthermore, we find an additional PdO interlayer in V2O5 nanodevices connected with a Pd/Au electrode after thermal annealing treatment. The PdO interlayer decreases the threshold voltages, and the Ion/ Ioff ratio increases because of the increased trap density of V2O5. These studies provide insights into V2O5 switching characteristics, which can support low power consumption in nonvolatile memory devices.

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