ABSTRACT
Correction for 'Interfacial engineering of a Mo/Hf0.3Zr0.7O2/Si capacitor using the direct scavenging effect of a thin Ti layer' by Se Hyun Kim et al., Chem. Commun., 2021, 57, 12452-12455, https://doi.org/10.1039/D1CC04966F.
ABSTRACT
Over the last few decades, the research on ferroelectric memories has been limited due to their dimensional scalability and incompatibility with complementary metal-oxide-semiconductor (CMOS) technology. The discovery of ferroelectricity in fluorite-structured oxides revived interest in the research on ferroelectric memories, by inducing nanoscale nonvolatility in state-of-the-art gate insulators by minute doping and thermal treatment. The potential of this approach has been demonstrated by the fabrication of sub-30 nm electronic devices. Nonetheless, to realize practical applications, various technical limitations, such as insufficient reliability including endurance, retention, and imprint, as well as large device-to-device-variation, require urgent solutions. Furthermore, such limitations should be considered based on targeting devices as well as applications. Various types of ferroelectric memories including ferroelectric random-access-memory, ferroelectric field-effect-transistor, and ferroelectric tunnel junction should be considered for classical nonvolatile memories as well as emerging neuromorphic computing and processing-in-memory. Therefore, from the viewpoint of materials science, this review covers the recent research focusing on ferroelectric memories from the history of conventional approaches to future prospects.
ABSTRACT
An antiferroelectric Mo/Hf0.3Zr0.7O2/SIOx/Si capacitor was engineered using the direct scavenging effect of a sputtered Ti sacrificial layer. Charge trapping could be mitigated with the oxidized TiO2 layer, and the endurance could be enhanced beyond 109 cycles, which is higher than that of the gate stack of ferroelectric field-effect-transistors by 3-4 orders of magnitude.
