CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

Correlation between PD-L1 expression status and efficacy of immunotherapy as second-line or later-line therapy in advanced non-small cell lung cancer patients.

OBJECTIVE: The objective of this study is to evaluate the correlation between tumor proportionality scores (TPS) and the effectiveness of immune checkpoint inhibitors (ICIs) as the second or subsequent line therapies for individuals who received diagnoses of advanced non-small cell lung cancer (NSCLC). METHODS: The retrospective analysis was conducted on the medical records of a total of 143 patients who received diagnoses of stage IIIB/IV NSCLC and were admitted to our hospital from the beginning of 2019 to the end of September 2022. The follow-up period ended on 01 January 2023. The study used Kaplan-Meier survival curves to assess the progression-free survival (PFS) and overall survival (OS) of patients. Univariate and multivariate Cox proportional risk models were used to analyze the factors associated with the PFS and OS of advanced-stage NSCLC patients who received ICIs as the second or subsequent lines. RESULTS: Patients diagnosed with NSCLC who had a TPS ≥1% and got treatment with ICIs exhibit notably elevated rates of partial response, objective response rate, disease control rate and extended PFS in comparison to NSCLC patients with a TPS of <1% (P < 0.05). NSCLC patients with TPS within 1-49% [hazard ratio (HR) = 0.372; 95% confidence interval (CI), 0.140-0.993; P = 0.048] or ≥50% (HR = 0.276; 95% CI, 0.095-0.796; P = 0.017) were significantly associated with prolonged PFS, which were conducted by multivariate Cox regression analysis. CONCLUSION: Programmed death protein-1 expression status may be predictive markers of the effectiveness of ICIs as the second or subsequent lines of therapies in advanced NSCLC are influenced by TPS.

Investigation on Recrystallization Channel for Vertical C-Shaped-Channel Nanosheet FETs by Laser Annealing.

Transistor scaling has become increasingly difficult in the dynamic random access memory (DRAM). However, vertical devices will be good candidates for 4F2 DRAM cell transistors (F = pitch/2). Most vertical devices are facing some technical challenges. For example, the gate length cannot be precisely controlled, and the gate and the source/drain of the device cannot be aligned. Recrystallization-based vertical C-shaped-channel nanosheet field-effect transistors (RC-VCNFETs) were fabricated. The critical process modules of the RC-VCNFETs were developed as well. The RC-VCNFET with a self-aligned gate structure has excellent device performance, and its subthreshold swing (SS) is 62.91 mV/dec. Drain-induced barrier lowering (DIBL) is 6.16 mV/V.

High-Quality Recrystallization of Amorphous Silicon on Si (100) Induced via Laser Annealing at the Nanoscale.

At sub-3 nm nodes, the scaling of lateral devices represented by a fin field-effect transistor (FinFET) and gate-all-around field effect transistors (GAAFET) faces increasing technical challenges. At the same time, the development of vertical devices in the three-dimensional direction has excellent potential for scaling. However, existing vertical devices face two technical challenges: "self-alignment of gate and channel" and "precise gate length control". A recrystallization-based vertical C-shaped-channel nanosheet field effect transistor (RC-VCNFET) was proposed, and related process modules were developed. The vertical nanosheet with an "exposed top" structure was successfully fabricated. Moreover, through physical characterization methods such as scanning electron microscopy (SEM), atomic force microscopy (AFM), conductive atomic force microscopy (C-AFM) and transmission electron microscopy (TEM), the influencing factors of the crystal structure of the vertical nanosheet were analyzed. This lays the foundation for fabricating high-performance and low-cost RC-VCNFETs devices in the future.

The linear impact of visual working memory load on visual awareness: Evidence from motion-induced blindness.

Despite the close relationship between visual working memory (VWM) and visual awareness, the question of how these two constructs interact with each other is still under debate. The current study aimed to further address this issue by investigating whether and how visual awareness is influenced by VWM load. In Experiment 1, participants were asked to perform a motion-induced blindness (MIB) task while simultaneously memorizing different numbers of items in VWM. The results indicated that the latency of MIB was prolonged gradually as the VWM load increased, revealing a linear trend in the modulation effect of VWM load on visual awareness. Experiments 2 and 3 tested the other potential explanations and validated the initial finding by confirming that VWM load was indeed responsible for the observed effect on visual awareness. These findings have important implications for a better understanding of the relationship between VWM and visual awareness.

Colorimetric/photothermal dual-mode sensing detection of ascorbic acid based on a Ag[i] ion/3,3',5,5'-tetramethylbenzidine (TMB) system.

In this work, a novel strategy of colorimetric and photothermal dual-mode sensing determination of ascorbic acid (AA) based on a Ag+/3,3',5,5'-tetramethylbenzidine (TMB) system was developed. In this sensing system, Ag+ could oxidize TMB with a distinct color change from colorless to blue color, strong absorbance at 652 nm and a photothermal effect under 808 nm laser irradiation due to the formation of oxidized TMB (oxTMB). When AA was present, oxTMB was reduced accompanied by a change from blue to colorless, and a decrease in absorption peak intensity and the photothermal effect. AA concentration showed a negative linear correlation with the value of both the absorbance intensity at 652 nm and temperature in the range of 0.2-10 µM (A = -0.03C + 0.343 (R 2, 0.9887; LOD, 50 nM); ΔT = -0.57C + 8.453 (R 2, 0.997; LOD, 7.8 nM)). Based on this, a sensing approach for detection of AA was proposed with dual-mode and without the complicated synthesis of nanomaterials. The photothermal effect and colorimetric signal provided a dual-mode detection strategy for AA, overcoming the limitations of any single mode. This colorimetric and photothermal dual-mode detection has great potential in the detection of AA in clinical pharmaceuticals and the construction of portable and highly sensitive sensors.

Reduced Dislocation of GaAs Layer Grown on Ge-Buffered Si (001) Substrate Using Dislocation Filter Layers for an O-Band InAs/GaAs Quantum Dot Narrow-Ridge Laser.

The development of the low dislocation density of the Si-based GaAs buffer is considered the key technical route for realizing InAs/GaAs quantum dot lasers for photonic integrated circuits. To prepare the high-quality GaAs layer on the Si substrate, we employed an engineered Ge-buffer on Si, used thermal cycle annealing, and introduced filtering layers, e.g., strained-layer superlattices, to control/reduce the threading dislocation density in the active part of the laser. In this way, a low defect density of 2.9 × 107 cm-2 could be achieved in the GaAs layer with a surface roughness of 1.01 nm. Transmission electron microscopy has been applied to study the effect of cycling, annealing, and filtering layers for blocking or bending threading-dislocation into the InAs QDs active region of the laser. In addition, the dependence of optical properties of InAs QDs on the growth temperature was also investigated. The results show that a density of 3.4 × 1010 InAs quantum dots could be grown at 450 °C, and the photoluminescence exhibits emission wavelengths of 1274 nm with a fullwidth at half-maximum (FWHM) equal to 32 nm at room temperature. The laser structure demonstrates a peak at 1.27 µm with an FWHM equal to 2.6 nm under a continuous-wave operation with a threshold current density of ∼158 A/cm2 for a 4-µm narrow-ridge width InAs QD device. This work, therefore, paves the path for a monolithic solution for photonic integrated circuits when III-V light sources (which is required for Si photonics) are grown on a Ge-platform (engineered Ge-buffer on Si) for the integration of the CMOS part with other photonic devices on the same chip in near future.

Monolithic Integration of O-Band InAs Quantum Dot Lasers with Engineered GaAs Virtual Substrate Based on Silicon.

The realization of high-performance Si-based III-V quantum-dot (QD) lasers has long attracted extensive interest in optoelectronic circuits. This manuscript presents InAs/GaAs QD lasers integrated on an advanced GaAs virtual substrate. The GaAs layer was originally grown on Ge as another virtual substrate on Si wafer. No patterned substrate or sophisticated superlattice defect-filtering layer was involved. Thanks to the improved quality of the comprehensively modified GaAs crystal with low defect density, the room temperature emission wavelength of this laser was allocated at 1320 nm, with a threshold current density of 24.4 A/cm-2 per layer and a maximum single-facet output power reaching 153 mW at 10 °C. The maximum operation temperature reaches 80 °C. This work provides a feasible and promising proposal for the integration of an efficient O-band laser with a standard Si platform in the near future.

Research on the Comprehensive Evaluation Method for the Automatic Recognition of Raman Spectrum under Multidimensional Constraint.

Raman spectrum contains abundant substance information with fingerprint characteristics. However, due to the huge variety of substances and their complex characteristic information, it is difficult to recognize the Raman spectrum accurately. Starting from dimensions like the Raman shift, the relative peak intensity, and the overall hit ratio of characteristic peaks, we extracted and recognized the characteristics in the Raman spectrum and analyzed these characteristics from local and global perspectives and then proposed a comprehensive evaluation method for the recognition of Raman spectrum on the basis of the data fusion of the recognition results under multidimensional constraint. Based on the common spectrum database of the normal Raman and surface-enhanced Raman of thousands of substances, we analyzed the performance of the evaluation method. It shows that even for the identification of spectra from instruments of low technical specifications, the automatic recognition rate of the sample can reach 98% and above, a great improvement compared with that of the common identification algorithms, which proves the effectiveness of the comprehensive evaluation method under multidimensional constraint.

Investigation of the Integration of Strained Ge Channel with Si-Based FinFETs.

In this manuscript, the integration of a strained Ge channel with Si-based FinFETs was investigated. The main focus was the preparation of high-aspect-ratio (AR) fin structures, appropriate etching topography and the growth of germanium (Ge) as a channel material with a highly compressive strain. Two etching methods, the wet etching and in situ HCl dry etching methods, were studied to achieve a better etching topography. In addition, the selective epitaxial growth of Ge material was performed on a patterned substrate using reduced pressure chemical vapor deposition. The results show that a V-shaped structure formed at the bottom of the dummy Si-fins using the wet etching method, which is beneficial to the suppression of dislocations. In addition, compressive strain was introduced to the Ge channel after the Ge selective epitaxial growth, which benefits the pMOS transport characteristics. The pattern dependency of the Ge growth over the patterned wafer was measured, and the solutions for uniform epitaxy are discussed.

Enhancement of InSe Field-Effect-Transistor Performance against Degradation of InSe Film in Air Environment.

The degradation of InSe film and its impact on field effect transistors are investigated. After the exposure to atmospheric environment, 2D InSe flakes produce irreversible degradation that cannot be stopped by the passivation layer of h-BN, causing a rapid decrease for InSe FETs performance, which is attributed to the large number of traps formed by the oxidation of 2D InSe and adsorption to impurities. The residual photoresist in lithography can cause unwanted doping to the material and reduce the performance of the device. To avoid contamination, a high-performance InSe FET is achieved by a using hard shadow mask instead of the lithography process. The high-quality channel surface is manifested by the hysteresis of the transfer characteristic curve. The hysteresis of InSe FET is less than 0.1 V at Vd of 0.2, 0.5, and 1 V. And a high on/off ratio of 1.25 × 108 is achieved, as well relative high Ion of 1.98 × 10-4 A and low SS of 70.4 mV/dec at Vd = 1 V are obtained, demonstrating the potential for InSe high-performance logic device.

Strain Modulation of Selectively and/or Globally Grown Ge Layers.

This article presents a novel method to grow a high-quality compressive-strain Ge epilayer on Si using the selective epitaxial growth (SEG) applying the RPCVD technique. The procedures are composed of a global growth of Ge layer on Si followed by a planarization using CMP as initial process steps. The growth parameters of the Ge layer were carefully optimized and after cycle-annealing treatments, the threading dislocation density (TDD) was reduced to 3 × 107 cm-2. As a result of this process, a tensile strain of 0.25% was induced, whereas the RMS value was as low as 0.81 nm. Later, these substrates were covered by an oxide layer and patterned to create trenches for selective epitaxy growth (SEG) of the Ge layer. In these structures, a type of compressive strain was formed in the SEG Ge top layer. The strain amount was -0.34%; meanwhile, the TDD and RMS surface roughness were 2 × 106 cm-2 and 0.68 nm, respectively. HRXRD and TEM results also verified the existence of compressive strain in selectively grown Ge layer. In contrast to the tensile strained Ge layer (globally grown), enhanced PL intensity by a factor of more than 2 is partially due to the improved material quality. The significantly high PL intensity is attributed to the improved crystalline quality of the selectively grown Ge layer. The change in direct bandgap energy of PL was observed, owing to the compressive strain introduced. Hall measurement shows that a selectively grown Ge layer possesses room temperature hole mobility up to 375 cm2/Vs, which is approximately 3 times larger than that of the Ge (132 cm2/Vs). Our work offers fundamental guidance for the growth of high-quality and compressive strain Ge epilayer on Si for future Ge-based optoelectronics integration applications.

Investigation of the Heteroepitaxial Process Optimization of Ge Layers on Si (001) by RPCVD.

This work presents the growth of high-quality Ge epilayers on Si (001) substrates using a reduced pressure chemical vapor deposition (RPCVD) chamber. Based on the initial nucleation, a low temperature high temperature (LT-HT) two-step approach, we systematically investigate the nucleation time and surface topography, influence of a LT-Ge buffer layer thickness, a HT-Ge growth temperature, layer thickness, and high temperature thermal treatment on the morphological and crystalline quality of the Ge epilayers. It is also a unique study in the initial growth of Ge epitaxy; the start point of the experiments includes Stranski-Krastanov mode in which the Ge wet layer is initially formed and later the growth is developed to form nuclides. Afterwards, a two-dimensional Ge layer is formed from the coalescing of the nuclides. The evolution of the strain from the beginning stage of the growth up to the full Ge layer has been investigated. Material characterization results show that Ge epilayer with 400 nm LT-Ge buffer layer features at least the root mean square (RMS) value and it's threading dislocation density (TDD) decreases by a factor of 2. In view of the 400 nm LT-Ge buffer layer, the 1000 nm Ge epilayer with HT-Ge growth temperature of 650 °C showed the best material quality, which is conducive to the merging of the crystals into a connected structure eventually forming a continuous and two-dimensional film. After increasing the thickness of Ge layer from 900 nm to 2000 nm, Ge surface roughness decreased first and then increased slowly (the RMS value for 1400 nm Ge layer was 0.81 nm). Finally, a high-temperature annealing process was carried out and high-quality Ge layer was obtained (TDD=2.78 × 107 cm-2). In addition, room temperature strong photoluminescence (PL) peak intensity and narrow full width at half maximum (11 meV) spectra further confirm the high crystalline quality of the Ge layer manufactured by this optimized process. This work highlights the inducing, increasing, and relaxing of the strain in the Ge buffer and the signature of the defect formation.

State of the Art and Future Perspectives in Advanced CMOS Technology.

The international technology roadmap of semiconductors (ITRS) is approaching the historical end point and we observe that the semiconductor industry is driving complementary metal oxide semiconductor (CMOS) further towards unknown zones. Today's transistors with 3D structure and integrated advanced strain engineering differ radically from the original planar 2D ones due to the scaling down of the gate and source/drain regions according to Moore's law. This article presents a review of new architectures, simulation methods, and process technology for nano-scale transistors on the approach to the end of ITRS technology. The discussions cover innovative methods, challenges and difficulties in device processing, as well as new metrology techniques that may appear in the near future.

Source information is inherently linked to working memory representation for auditory but not for visual stimuli.

Failing to remember the source of retrievable information is known as source amnesia. This phenomenon has been extensively investigated in long-term memory but rarely in working memory, as we share the intuition that the source information of an item that we have encountered in the immediate past is always available. However, a recent study (Chen, Carlson, & Wyble, 2018) challenged this common sense by showing the source amnesia for simple visual stimuli (e.g., colored square) in the context of working memory when participants did not expect having to report source information, which indicated that the source information of visual stimuli was not automatically encoded into working memory. The current study sought to further examine this newly discovered phenomenon by testing whether it persists with complex and meaningful stimuli in the visual modality (Experiments 1, 4a & 4b), cross-visual-and-auditory modalities (Experiments 2a & 2b), and within-auditory modality (Experiment 3). Interestingly, the results revealed that short-term source amnesia was a robust effect in the visual modality even for complex and meaningful stimuli, whereas it was absent in the cross-visual-and-auditory or within-auditory modalities, regardless of reporting expectation. This indicates differences in working memory representations of visual and auditory stimuli, namely, the representation of auditory stimuli was stored together with the corresponding original sources, while that of visual stimuli was stored independently of its source information. These findings have crucial implications for further clarifying the longstanding debate regarding whether or not there is a modality-independent working memory storage system for different modalities.

Miniaturization of CMOS.

When the international technology roadmap of semiconductors (ITRS) started almost five decades ago, the metal oxide effect transistor (MOSFET) as units in integrated circuits (IC) continuously miniaturized. The transistor structure has radically changed from its original planar 2D architecture to today's 3D Fin field-effect transistors (FinFETs) along with new designs for gate and source/drain regions and applying strain engineering. This article presents how the MOSFET structure and process have been changed (or modified) to follow the More Moore strategy. A focus has been on methodologies, challenges, and difficulties when ITRS approaches the end. The discussions extend to new channel materials beyond the Moore era.

Does attribute amnesia occur with the presentation of complex, meaningful stimuli? The answer is, "it depends".

Attribute amnesia (AA) is a recently reported phenomenon whereby participants are unable to report a salient attribute of a stimulus (e.g., the color or identity of a target letter) on which their attention has just been focused during a prior task. This counterintuitive effect has been repeatedly replicated with various simple stimuli such as digits and letters. The current study sought to explore boundaries of AA by investigating whether the phenomenon persists when participants encounter complex, meaningful stimuli (e.g., pictures) that have been shown to hold an advantage in cognitive processing and memory. In Experiments 1a-d, we examined whether AA was observed with different types of complex stimuli. In Experiments 2a-b and 3a-b, we linked the type of stimuli (simple vs. complex and meaningful stimuli) to the other two potential boundary factors of AA (i.e., repetitiveness of target stimulus and set effects of Einstellung) to see whether there were interactions between stimuli type and these two boundary factors. The results demonstrated that the AA effect was still consistently observed for complex stimuli in a typical AA paradigm wherein participants encountered many trials and the targets were repeated across trials. However, this effect only appeared for simple stimuli, but not for complex stimuli in two special cases: when target stimuli were never repeated through the experiment, or when the surprise test was placed on the first trial of the experiment. These findings have crucial implications in understanding the boundaries of the AA phenomenon.

Near-ideal subthreshold swing MoS2 back-gate transistors with an optimized ultrathin HfO2 dielectric layer.

In this paper, a near-ideal subthreshold swing MoS2 back-gate transistor with an optimized ultrathin HfO2 dielectric layer is reported with detailed physical and electrical characteristics analyses. Ultrathin (10 nm) HfO2 films created by atomic-layer deposition (ALD) at a low temperature with rapid-thermal annealing (RTA) at different temperatures from 200 °C to 800 °C have a great effect on the electrical characteristics, such as the subthreshold swing (SS), on-to-off current (I ON/I OFF) ratio, etc, of the MoS2 devices. Physical examinations are performed, including x-ray diffraction, atomic force microscopy, and electrical experiments of metal-oxide-semiconductor capacitance-voltage. The results demonstrate a strong correlation between the HfO2 dielectric RTA temperature and the film characteristics, such as film density, crystallization degree, grain size and surface states, inducing a variation in the electrical parameters, such as the leakage, D it, equivalent oxide thickness, SS, and I ON, as well as I ON/I OFF of the MoS2 field effect transistors with the same channel materials and fabrication methods. With a balance between the crystallization degree and the surface state, the ultrathin (10 nm) HfO2 gate dielectric RTA at 500 °C is demonstrated to have the best performance with a field effect mobility of 40 cm2 V-1 s-1 and the lowest SS of 77.6 mV-1 decade, which are superior to those of the control samples at other temperatures. The excellent transistor results with an optimized industry-based HfO2 ALD and RTA process provide a promising approach for MoS2 applications into the scaling of the nanoscale CMOS process.

Inverted process for graphene integrated circuits fabrication.

CMOS compatible 200 mm two-layer-routing technology is employed to fabricate graphene field-effect transistors (GFETs) and monolithic graphene ICs. The process is inverse to traditional Si technology. Passive elements are fabricated in the first metal layer and GFETs are formed with buried gate/source/drain in the second metal layer. Gate dielectric of 3.1 nm in equivalent oxide thickness (EOT) is employed. 500 nm-gate-length GFETs feature a yield of 80% and fT/fmax = 17 GHz/15.2 GHz RF performance. A high-performance monolithic graphene frequency multiplier is demonstrated using the proposed process. Functionality was demonstrated up to 8 GHz input and 16 GHz output. The frequency multiplier features a 3 dB bandwidth of 4 GHz and conversion gain of -26 dB.