Memristor-based analogue computing for brain-inspired sound localization with in situ training.

The human nervous system senses the physical world in an analogue but efficient way. As a crucial ability of the human brain, sound localization is a representative analogue computing task and often employed in virtual auditory systems. Different from well-demonstrated classification applications, all output neurons in localization tasks contribute to the predicted direction, introducing much higher challenges for hardware demonstration with memristor arrays. In this work, with the proposed multi-threshold-update scheme, we experimentally demonstrate the in-situ learning ability of the sound localization function in a 1K analogue memristor array. The experimental and evaluation results reveal that the scheme improves the training accuracy by ∼45.7% compared to the existing method and reduces the energy consumption by ∼184× relative to the previous work. This work represents a significant advance towards memristor-based auditory localization system with low energy consumption and high performance.

Application of mathematical morphology operation with memristor-based computation-in-memory architecture for detecting manufacturing defects.

Mathematical morphology operations are widely used in image processing such as defect analysis in semiconductor manufacturing and medical image analysis. These data-intensive applications have high requirements during hardware implementation that are challenging for conventional hardware platforms such as central processing units (CPUs) and graphics processing units (GPUs). Computation-in-memory (CIM) provides a possible solution for highly efficient morphology operations. In this study, we demonstrate the application of morphology operation with a novel memristor-based auto-detection architecture and demonstrate non-neuromorphic computation on a multi-array-based memristor system. Pixel-by-pixel logic computations with low parallelism are converted to parallel operations using memristors. Moreover, hardware-implemented computer-integrated manufacturing was used to experimentally demonstrate typical defect detection tasks in integrated circuit (IC) manufacturing and medical image analysis. In addition, we developed a new implementation scheme employing a four-layer network to realize small-object detection with high parallelism. The system benchmark based on the hardware measurement results showed significant improvement in the energy efficiency by approximately 358 times and 32 times more than when a CPU and GPU were employed, respectively, exhibiting the advantage of the proposed memristor-based morphology operation.

Ratio-based multi-level resistive memory cells.

Ratio-based encoding has recently been proposed for single-level resistive memory cells, in which the resistance ratio of a pair of resistance-switching devices, rather than the resistance of a single device (i.e. resistance-based encoding), is used for encoding single-bit information, which significantly reduces the bit error probability. Generalizing this concept for multi-level cells, we propose a ratio-based information encoding mechanism and demonstrate its advantages over the resistance-based encoding for designing multi-level memory systems. We derive a closed-form expression for the bit error probability of ratio-based and resistance-based encodings as a function of the number of levels of the memory cell, the variance of the distribution of the resistive states, and the ON/OFF ratio of the resistive device, from which we prove that for a multi-level memory system using resistance-based encoding with bit error probability x, its corresponding bit error probability using ratio-based encoding will be reduced to [Formula: see text] at the best case and [Formula: see text] at the worst case. We experimentally validated these findings on multiple resistance-switching devices and show that, compared to the resistance-based encoding on the same resistive devices, our approach achieves up to 3 orders of magnitude lower bit error probability, or alternatively it could reduce the cell's programming time and programming energy by up 5-10[Formula: see text], while achieving the same bit error probability.

A Threshold Switching Selector Based on Highly Ordered Ag Nanodots for X-Point Memory Applications.

Leakage interference between memory cells is the primary obstacle for enlarging X-point memory arrays. Metal-filament threshold switches, possessing excellent selectivity and low leakage current, are developed in series with memory cells to reduce sneak path current and lower power consumption. However, these selectors typically have limited on-state currents (≤10 µA), which are insufficient for memory RESET operations. Here, a strategy is proposed to achieve sufficiently large RESET current (≈2.3 mA) by introducing highly ordered Ag nanodots to the threshold switch. Compared to the Ag thin film case, Ag nanodots as active electrode could avoid excessive Ag atoms migration into solid electrolyte during operations, which causes stable conductive filament growth. Furthermore, Ag nanodots with rapid thermal processing contribute to forming multiple weak Ag filaments at a lower voltage and then spontaneous rupture as the applied voltage reduced, according to quantized conductance and simulation analysis. Impressively, the Ag nanodots based threshold switch, which is bidirectional and truly electroforming-free, demonstrates extremely high selectivity >109, ultralow leakage current <1 pA, very steep slope of 0.65 mV dec-1, and good thermal stability up to 200 °C, and further represents significant suppression of leakage currents and excellent performances for SET/RESET operations in the one-selector-one-resistor configuration.