ABSTRACT
In this paper, thermoreflectance microscopy was used to measure the high spatial resolution temperature distribution of the p-GaN HEMT under high power density. The maximum temperature along the GaN channel was located at the drain-side gate edge region. It was found that the thermal resistance (Rth) of the p-GaN HEMT device increased with the increase of channel temperature. The Rth dependence on the temperature was well approximated by a function of Rth~Ta (a = 0.2). The three phonon Umklapp scattering, point mass defects and dislocations scattering mechanisms are suggested contributors to the heat transfer process for the p-GaN HEMT. The impact of bias conditions and gate length on the thermal characteristics of the device was investigated. The behaviour of temperature increasing in the time domain with 50 µs pulse width and different drain bias voltage was analysed. Finally, a field plate structure was demonstrated for improving the device thermal performance.
ABSTRACT
The past decades have witnessed a tremendous development of GaN-based power electronic devices grown on Si substrate. This article provides a concise introduction, review, and outlook of the research developments of GaN-on-Si power device technology. The comprehensive review has discussed the crucial issues in the state-of-the-art device technology based on both GaN materials epitaxy including stress control and point defects study, and device fabrication including normally off solutions like Cascode, trench MIS-gate, and p-GaN gate. Device reliability and other common fabrication issues in GaN high electron mobility transistors (HEMTs) are also discussed. Lastly, we give an outlook on the GaN-on-Si power devices from two aspects, namely high frequency, and high power GaN ICs, and GaN vertical power devices.
ABSTRACT
This work studied the effect of thermal cleaning in metal-organic chemical vapor deposition (MOCVD) prior to p-GaN gate regrowth for normally off high-electron-mobility transistors. X-ray photoelectron spectroscopy, capacitance-voltage measurement, and atomic force microscopy were employed to identify the effects of thermal cleaning before p-GaN regrowth. It was found that the residual damage was hardly repaired at a relatively low thermal cleaning temperature, while GaN decomposition would occur at an excessively high temperature. Thermal cleaning at 850 °C for 2 min in MOCVD can effectively remove the surface contamination and alleviate the etch damage without causing any significant deterioration of the AlGaN barrier. In addition, the density of interface states ( Dit) in the p-GaN gate was reduced from 1012-1013 to 1011-1012 eV-1·cm-2, resulting in a low gate reverse leakage of 0.1 nA/mm @ VDS-OFF = 180 V, a high Ion/ Ioff ratio of 4 × 1010, and a relatively high threshold voltage of +1.7 V @ ID = 10 µA/mm.
ABSTRACT
Direct bandgap III-V semiconductor lasers grown on silicon (Si) are highly desired for monolithic integration with Si photonics. Fabrication of semiconductor lasers with a Fabry-Pérot cavity usually includes facet cleavage, however, that is not compatible with on-chip photonic integration. Etching as an alternative approach holds a great advantage in preparing cavity mirrors with no need of breaking wafer into bars. However, gallium nitride (GaN) sidewalls prepared by dry etching often have a large roughness and etching damages, which would cause mirror loss due to optical scattering and carrier injection loss because of surface non-radiative recombination. A wet chemical polishing process of GaN sidewall facets formed by dry etching was studied in detail to remove the etching damages and smooth the vertical sidewalls. The wet chemical polishing technique combined with dry etching was successfully applied to the on-wafer fabrication of cavity mirrors, which enabled the realization of room temperature electrically injected InGaN-based laser diodes grown on Si.
