III-V heterostructure tunnel field-effect transistor.

The tunnel field-effect transistor (TFET) is regarded as one of the most promising solid-state switches to overcome the power dissipation challenge in ultra-low power integrated circuits. TFETs take advantage of quantum mechanical tunneling hence exploit a different current control mechanism compared to standard MOSFETs. In this review, we describe state-of-the-art development of TFET both in terms of performances and of materials integration and we identify the main remaining technological challenges such as heterojunction defects and oxide/channel interface traps causing trap-assisted-tunneling (TAT). Mesa-structures, planar as well as vertical geometries are examined. Conductance slope analysis on InAs/GaSb nanowire tunnel diodes are reported, these two-terminal measurements can be relevant to investigate the tunneling behavior. A special focus is dedicated to III-V heterostructure TFET, as different groups have recently shown encouraging results achieving the predicted sub-thermionic low-voltage operation.

Gated Hall effect measurements on selectively grown InGaAs nanowires.

InGaAs nanowires is one of the promising material systems of replacing silicon in future CMOS transistors, due to its high electron mobility in combination with the excellent electrostatic control from the tri-gate geometry. In this article, we report on gated Hall measurements on single and multiple In0.85Ga0.15As nanowires, selectively grown in a Hall bridge geometry with nanowire widths down to 50 nm and thicknesses of 10 nm. The gated nanowires can be used as junctionless transistors, which allows for a simplified device processing as no regrowth of contact layer or ion implantation is needed, which is particularly beneficial as transistor dimensions are scaled down. The analysis shows that the InGaAs layer has a carrier concentration of above 1019 cm-3, with a Hall carrier mobility of around 1000 cm2 V-1 s-1. The gated Hall measurements reveal an increased carrier concentration as a function of applied gate voltage, with an increasing mobility for narrow nanowires but no significant effect on larger nanowires.