Electron Beam Effects on Oxide Thin Films-Structure and Electrical Property Correlations.

In situ transmission electron microscope (TEM) characterization techniques provide valuable information on structure-property correlations to understand the behavior of materials at the nanoscale. However, understanding nanoscale structures and their interaction with the electron beam is pivotal for the reliable interpretation of in situ/ex situ TEM studies. Here, we report that oxides commonly used in nanoelectronic applications, such as transistor gate oxides or memristive devices, are prone to electron beam induced damage that causes small structural changes even under very low dose conditions, eventually changing their electrical properties as examined via in situ measurements. In this work, silicon, titanium, and niobium oxide thin films are used for in situ TEM electrical characterization studies. The electron beam induced reduction of the oxides turns these insulators into conductors. The conductivity change is reversible by exposure to air, supporting the idea of electron beam reduction of oxides as primary damage mechanism. Through these measurements we propose a limit for the critical dose to be considered for in situ scanning electron microscopy and TEM characterization studies.

Sub-50 nm Channel Vertical Field-Effect Transistors using Conventional Ink-Jet Printing.

A printed vertical field-effect transistor is demonstrated, which decouples critical device dimensions from printing resolution. A printed mesoporous semiconductor layer, sandwiched between vertically stacked drive electrodes, provides <50 nm channel lengths. A polymer-electrolyte-based gate insulator infiltrates the percolating pores of the mesoporous channel to accumulate charge carriers at every semiconductor domain, thereby, resulting in an unprecedented current density of MA cm-2 .

Temperature-Dependent Performance of Printed Field-Effect Transistors with Solid Polymer Electrolyte Gating.

Printable, physical, and air-stable composite solid polymer electrolytes (CSPEs) with high ionic conductivity have been established as a suitable alternative to standard dielectric gate insulators for printed field-effect transistors (FETs) and logics. We have performed a stress and temperature stability study involving several CSPEs. Mechanical tensile and shear tests have been performed to determine the physical condition of CSPEs. A comprehensive temperature dependent study has been conducted within the working temperature range which electric double layer (EDL) capacitors or CSPE-gated FETs may typically experience during their lifetime. Moreover, calorimetric measurements have been performed to investigate the CSPEs stability, especially at low temperatures. Mechanical characterizations have shown tensile strength and shear modulus of the material that is typical for solid polymer electrolytes while DSC measurements show no change in the physical state within the measured temperature range. An expected increase in ionic conductivity of the CSPEs of nearly 1 order of magnitude has been observed with an increase in temperature, while an anomalous positive temperature relationship to EDL capacitance has also been noticed. Interestingly, the transistor performance characteristics, namely, on-current and threshold voltage, are found to be quite independent of the temperature, thus ensuring a large and stable operation temperature window for CSPE-gated FETs. The other parameters, subthreshold slope and the device mobility, have varied following the classical semiconductor behavior. In fact, the present study not only provides a detailed understanding of temperature dependence of the CSPE-gated FETs but also offers an insight into the physical and electrical properties of the CSPEs itself. Therefore, these results may very well help to comprehend and improve EDL capacitors, supercapacitors, and other devices that use CSPEs as the active material.

Facile fabrication of electrolyte-gated single-crystalline cuprous oxide nanowire field-effect transistors.

Oxide semiconductors are considered to be one of the forefront candidates for the new generation, high-performance electronics. However, one of the major limitations for oxide electronics is the scarcity of an equally good hole-conducting semiconductor, which can provide identical performance for the p-type metal oxide semiconductor field-effect transistors as compared to their electron conducting counterparts. In this quest, here we present a bulk synthesis method for single crystalline cuprous oxide (Cu2O) nanowires, their chemical and morphological characterization and suitability as active channel material in electrolyte-gated, low-power, field-effect transistors (FETs) for portable and flexible logic circuits. The bulk synthesis method used in the present study includes two steps: namely hydrothermal synthesis of the nanowires and the removal of the surface organic contaminants. The surface treated nanowires are then dispersed on a receiver substrate where the passive electrodes are structured, followed by printing of a composite solid polymer electrolyte (CSPE), chosen as the gate insulator. The characteristic electrical properties of individual nanowire FETs are found to be quite interesting including accumulation-mode operation and field-effect mobility of 0.15 cm(2) V(-1) s(-1).