Highly Sensitive Active-Matrix Driven Self-Capacitive Fingerprint Sensor based on Oxide Thin Film Transistor.

The fingerprint recognition has been widely used for biometrics in mobile devices. Existing fingerprint sensors have already been commercialized in the field of mobile devices using primarily Si-based technologies. Recently, mutual-capacitive fingerprint sensors have been developed to lower production costs and expand the range of application using thin-film technologies. However, since the mutual-capacitive method detects the change of mutual capacitance, it has high ratio of parasitic capacitance to ridge-to-valley capacitance, resulting in low sensitivity, compared to the self-capacitive method. In order to demonstrate the self-capacitive fingerprint sensor, a switching device such as a transistor should be integrated in each pixel, which reduces a complexity of electrode configuration and sensing circuits. The oxide thin-film transistor (TFT) can be a good candidate as a switching device for the self-capacitive fingerprint sensor. In this work, we report a systematic approach for self-capacitive fingerprint sensor integrating Al-InSnZnO TFTs with field-effect mobility higher than 30 cm2/Vs, which enable isolation between pixels, by employing industry-friendly process methods. The fingerprint sensors are designed to reduce parasitic resistance and capacitance in terms of the entire system. The excellent uniformity and low leakage current (<10-12) of the oxide TFTs allow successful capture of a fingerprint image.

Low-Power Low-Noise Amplifier Using Attenuation-Adaptive Noise Control for Ultrasound Imaging Systems.

This paper presents a low-noise amplifier (LNA) using attenuation-adaptive noise control (AANC) for ultrasound imaging systems. The proposed AANC reduces unnecessary power consumption of the LNA, which arises from useless noise floor, by controlling the noise floor of the LNA with respect to the attenuation of the ultrasound. In addition, a current feedback amplifier with a source-degenerated input stage reduces variations of the bandwidth and the closed loop gain, which are caused by the AANC. The proposed LNA was fabricated using a 0.18-[Formula: see text] CMOS process. The input-referred voltage noise density of the fabricated LNA is 1.01 [Formula: see text] at the frequency of 5 MHz. The second harmonic distortion is -53.5 dB when the input signal frequency is 5 MHz and the output voltage swing is 2 [Formula: see text]. The power consumption of the LNA using the AANC is 16.2 mW at the supply voltage of 1.8 V, which is reduced to 64% of that without using the AANC. The noise efficiency factor (NEF) of the proposed LNA is 3.69, to our knowledge, which is the lowest NEF compared with previous LNAs for ultrasound imaging.

A Readout IC Using Two-Step Fastest Signal Identification for Compact Data Acquisition of PET Systems.

A readout integrated circuit (ROIC) using two-step fastest signal identification (FSI) is proposed to reduce the number of input channels of a data acquisition (DAQ) block with a high-channel reduction ratio. The two-step FSI enables the proposed ROIC to filter out useless input signals that arise from scattering and electrical noise without using complex and bulky circuits. In addition, an asynchronous fastest signal identifier and a self-trimmed comparator are proposed to identify the fastest signal without using a high-frequency clock and to reduce misidentification, respectively. The channel reduction ratio of the proposed ROIC is 16:1 and can be extended to 16 × N:1 using N ROICs. To verify the performance of the two-step FSI, the proposed ROIC was implemented into a gamma photon detector module using a Geiger-mode avalanche photodiode with a lutetium-yttrium oxyorthosilicate array. The measured minimum detectable time is 1 ns. The difference of the measured energy and timing resolution between with and without the two-step FSI are 0.8% and 0.2 ns, respectively, which are negligibly small. These measurement results show that the proposed ROIC using the two-step FSI reduces the number of input channels of the DAQ block without sacrificing the performance of the positron emission tomography (PET) systems.

A Fast Multiple Sampling Method for Low-Noise CMOS Image Sensors With Column-Parallel 12-bit SAR ADCs.

This paper presents a fast multiple sampling method for low-noise CMOS image sensor (CIS) applications with column-parallel successive approximation register analog-to-digital converters (SAR ADCs). The 12-bit SAR ADC using the proposed multiple sampling method decreases the A/D conversion time by repeatedly converting a pixel output to 4-bit after the first 12-bit A/D conversion, reducing noise of the CIS by one over the square root of the number of samplings. The area of the 12-bit SAR ADC is reduced by using a 10-bit capacitor digital-to-analog converter (DAC) with four scaled reference voltages. In addition, a simple up/down counter-based digital processing logic is proposed to perform complex calculations for multiple sampling and digital correlated double sampling. To verify the proposed multiple sampling method, a 256 × 128 pixel array CIS with 12-bit SAR ADCs was fabricated using 0.18 µm CMOS process. The measurement results shows that the proposed multiple sampling method reduces each A/D conversion time from 1.2 µs to 0.45 µs and random noise from 848.3 µV to 270.4 µV, achieving a dynamic range of 68.1 dB and an SNR of 39.2 dB.

Bone-induced streak artifact suppression in sparse-view CT image reconstruction.

BACKGROUND: In sparse-view CT imaging, strong streak artifacts may appear around bony structures and they often compromise the image readability. Compressed sensing (CS) or total variation (TV) minimization-based image reconstruction method has reduced the streak artifacts to a great extent, but, sparse-view CT imaging still suffers from residual streak artifacts. We introduce a new bone-induced streak artifact reduction method in the CS-based image reconstruction. METHODS: We firstly identify the high-intensity bony regions from the image reconstructed by the filtered backprojection (FBP) method, and we calculate the sinogram stemming from the bony regions only. Then, we subtract the calculated sinogram, which stands for the bony regions, from the measured sinogram before performing the CS-based image reconstruction. The image reconstructed from the subtracted sinogram will stand for the soft tissues with little streak artifacts on it. To restore the original image intensity in the bony regions, we add the bony region image, which has been identified from the FBP image, to the soft tissue image to form a combined image. Then, we perform the CS-based image reconstruction again on the measured sinogram using the combined image as the initial condition of the iteration. For experimental validation of the proposed method, we take images of a contrast phantom and a rat using a micro-CT and we evaluate the reconstructed images based on two figures of merit, relative mean square error and total variation caused by the streak artifacts. RESULTS: The images reconstructed by the proposed method have been found to have smaller streak artifacts than the ones reconstructed by the original CS-based method when visually inspected. The quantitative image evaluation studies have also shown that the proposed method outperforms the conventional CS-based method. CONCLUSIONS: The proposed method can effectively suppress streak artifacts stemming from bony structures in sparse-view CT imaging.

A nanowire-based shift register for display scan drivers.

The development of display scan drivers is an essential step in the effort to develop transparent and flexible display devices based on nanowire transistors. Here we report a transparent nanowire-based shift register that functions as the standard logic circuit of a display scan driver. To form the shift register circuits using only n-type nanowire transistors, a novel circuit structure was introduced to avoid the output voltage drop typical of purely n-type circuits. A circuit simulation based on the measured nanowire transistor characteristics was developed in the planning phase to verify the circuit operation of the shift register. The shift register successfully produced an output of 0-3 V without an output voltage drop while applying an input of 3 V peak to peak. In addition, the shift register was designed to have multiple channels with a randomly oriented nanowire placement method to enhance the operation yield.