A False Trigger-Strengthened and Area-Saving Power-Rail Clamp Circuit with High ESD Performance.

A power clamp circuit, which has good immunity to false trigger under fast power-on conditions with a 20 ns rising edge, is proposed in this paper. The proposed circuit has a separate detection component and an on-time control component which enable it to distinguish between electrostatic discharge (ESD) events and fast power-on events. As opposed to other on-time control techniques, instead of large resistors or capacitors, which can cause a large occupation of the layout area, we use a capacitive voltage-biased p-channel MOSFET in the on-time control part of the proposed circuit. The capacitive voltage-biased p-channel MOSFET is in the saturation region after the ESD event is detected, which can serve as a large equivalent resistance (~106 Ω) in the structure. The proposed power clamp circuit offers several advantages compared to the traditional circuit, such as having at least 70% area savings in the trigger circuit area (30% area savings in the whole circuit area), supporting a power supply ramp time as fast as 20 ns, dissipating the ESD energy more cleanly with little residual charge, and recovering faster from false triggers. The rail clamp circuit also offers robust performance in an industry-standard PVT (process, voltage, and temperature) space and has been verified by the simulation results. Showing good performance of human body model (HBM) endurance and high immunity to false trigger, the proposed power clamp circuit has great potential for application in ESD protection.

Analysis and Hardening of SEGR in Trench VDMOS with Termination Structure.

Single-event gate-rupture (SEGR) in the trench vertical double-diffused power MOSFET (VDMOS) occurs at a critical bias voltage during heavy-ion experiments. Fault analysis demonstrates that the hot spot is located at the termination of the VDMOS, and the gate oxide in the termination region has been damaged. The SEGR-hardened termination with multiple implantation regions is proposed and simulated using the Sentaurus TCAD. The multiple implantation regions are introduced, leading to an increase in the distance between the gate oxide and the hole accumulation region, as well as a decrease in the resistivity of the hole conductive path. This approach is effective in reducing the electric field of the gate oxide to below the calculated critical field, and results in a lower electric field than the conventional termination.