A Chip Integrity Monitor for Evaluating Moisture/Ion Ingress in mm-Sized Single-Chip Implants.

For mm-sized implants incorporating silicon integrated circuits, ensuring lifetime operation of the chip within the corrosive environment of the body still remains a critical challenge. For the chip's packaging, various polymeric and thin ceramic coatings have been reported, demonstrating high biocompatibility and barrier properties. Yet, for the evaluation of the packaging and lifetime prediction, the conventional helium leak test method can no longer be applied due to the mm-size of such implants. Alternatively, accelerated soak studies are typically used instead. For such studies, early detection of moisture/ion ingress using an in-situ platform may result in a better prediction of lifetime functionality. In this work, we have developed such a platform on a CMOS chip. Ingress of moisture/ions would result in changes in the resistance of the interlayer dielectrics (ILD) used within the chip and can be tracked using the proposed system, which consists of a sensing array and an on-chip measurement engine. The measurement system uses a novel charge/discharge based time-mode resistance sensor that can be implemented using simple yet highly robust circuitry. The sensor array is implemented together with the measurement engine in a standard 0.18  µm 6-metal CMOS process. The platform was validated through a series of dry and wet measurements. The system can measure the ILD resistance with values of up to 0.504 peta-ohms, with controllable measurement steps that can be as low as 0.8 M Ω. The system works with a supply voltage of 1.8 V, and consumes 4.78 mA. Wet measurements in saline demonstrated the sensitivity of the platform in detecting moisture/ion ingress. Such a platform could be used both in accelerated soak studies and during the implant's life-time for monitoring the integrity of the chip's packaging.

High-level energy estimation in the sub-VT domain: simulation and measurement of a cardiac event detector.

This paper presents a flow that is suitable to estimate energy dissipation of digital standard-cell based designs which are determined to operate in the subthreshold regime. The flow is applicable on gate-level netlists, where back-annotated toggle information is used to find the minimum energy operation point, corresponding maximum clock frequency, as well as the dissipated energy per clock cycle. The application of the model is demonstrated by exploring the energy efficiency of pipelining, retiming, and register balancing. Simulation results, which are obtained during a fraction of SPICE simulation time, are validated by measurements on a wavelet-based cardiac event detector that was fabricated in 65-nm low-leakage high-threshold technology. The mean of the absolute modeling error is calculated as 5.2%, with a standard deviation of 6.6% over the measurement points. The cardiac event detector dissipates 0.88 pJ/sample at a supply voltage of 320 mV.