Growth of 2D Materials at the Wafer Scale.

Wafer-scale growth has become a critical bottleneck for scaling up applications of van der Waal (vdW) layered 2D materials in high-end electronics and optoelectronics. Most vdW 2D materials are initially obtained through top-down synthesis methods, such as exfoliation, which can only prepare small flakes on a micrometer scale. Bottom-up growth can enable 2D flake growth over a large area. However, seamless merging of these flakes to form large-area continuous films with well-controlled layer thickness and lattice orientation is still a significant challenge. This review briefly introduces several vdW layered 2D materials covering their lattice structures, representative physical properties, and potential roles in large-scale applications. Then, several methods used to grow vdW layered 2D materials at the wafer scale are reviewed in depth. In particular, three strategies are summarized that enable 2D film growth with a single-crystalline structure over the whole wafer: growth of an isolated domain, growth of unidirectional domains, and conversion of oriented precursors. After that, the progress in using wafer-scale 2D materials in integrated devices and advanced epitaxy is reviewed. Finally, future directions in the growth and scaling of vdW layered 2D materials are discussed.

High-Yield Ti3 C2 Tx MXene-MoS2 Integrated Circuits.

It is very challenging to employ solution-processed conducting films in large-area ultrathin nanoelectronics. Here, spray-coated Ti3 C2 Tx MXene films as metal contacts are successfully integrated into sub-10 nm gate oxide 2D MoS2 transistor circuits. Ti3 C2 Tx films are spray coated on glass substrates followed by vacuum annealing. Compared to the as-prepared sample, vacuum annealed films exhibit a higher conductivity (≈11 000 S cm-1 ) and a lower work function (≈4.5 eV). Besides, the annealed Ti3 C2 Tx film can be patterned through a standard cleanroom process without peeling off. The annealed Ti3 C2 Tx film shows a better band alignment for n-type transport in MoS2 channel with small work function mismatch of 0.06 eV. The MoS2 film can be uniformly transferred on the patterned Ti3 C2 Tx surface and then readily processed through the cleanroom process. A large-area array of Ti3 C2 Tx MXene-MoS2 transistors is fabricated using different dielectric thicknesses and semiconducting channel sizes. High yield and stable performance for these transistor arrays even with an 8 nm-thick dielectric layer are demonstrated. Besides, several circuits are demonstrated, including rectifiers, negative-channel metal-oxide-semiconductor (NMOS) inverters, and voltage-shift NMOS inverters. Overall, this work indicates the tremendous potential for solution-processed Ti3 C2 Tx MXene films in large-area 2D nanoelectronics.