Antiferroelectric negative capacitance from a structural phase transition in zirconia.

Crystalline materials with broken inversion symmetry can exhibit a spontaneous electric polarization, which originates from a microscopic electric dipole moment. Long-range polar or anti-polar order of such permanent dipoles gives rise to ferroelectricity or antiferroelectricity, respectively. However, the recently discovered antiferroelectrics of fluorite structure (HfO2 and ZrO2) are different: A non-polar phase transforms into a polar phase by spontaneous inversion symmetry breaking upon the application of an electric field. Here, we show that this structural transition in antiferroelectric ZrO2 gives rise to a negative capacitance, which is promising for overcoming the fundamental limits of energy efficiency in electronics. Our findings provide insight into the thermodynamically forbidden region of the antiferroelectric transition in ZrO2 and extend the concept of negative capacitance beyond ferroelectricity. This shows that negative capacitance is a more general phenomenon than previously thought and can be expected in a much broader range of materials exhibiting structural phase transitions.

Integration of InGaAs MOSFETs and GaAs/ AlGaAs lasers on Si Substrate for advanced opto-electronic integrated circuits (OEICs).

Lasers monolithically integrated with high speed MOSFETs on the silicon (Si) substrate could be a key to realize low cost, low power, and high speed opto-electronic integrated circuits (OEICs). In this paper, we report the monolithic integration of InGaAs channel transistors with electrically pumped GaAs/AlGaAs lasers on the Si substrate for future advanced OEICs. The laser and transistor layers were grown on the Si substrate by molecular beam epitaxy (MBE) using direct epitaxial growth. InGaAs n-FETs with an ION/IOFF ratio of more than 106 with very low off-state leakage and a low subthreshold swing with a minimum of 82 mV/decade were realized. Electrically pumped GaAs/AlGaAs quantum well (QW) lasers with a lasing wavelength of 795 nm at room temperature were demonstrated. The overall fabrication process has a low thermal budget of no more than 400 °C.

Monolithic integration of InGaAs n-FETs and lasers on Ge substrate.

We report the first monolithic integration of InGaAs channel field-effect transistors with InGaAs/GaAs multiple quantum wells (MQWs) lasers on a common platform, achieving a milestone in the path of enabling low power and high speed opto-electronic integrated circuits (OEICs). The III-V layers used for realizing transistors and lasers were grown epitaxially on the Ge substrate using molecular beam epitaxy (MBE). A Si-CMOS compatible process was developed to realize InGaAs n-FETs with subthreshold swing SS of 93 mV/decade, ION/IOFF ratio of more than 4 orders of magnitude with very low off-state leakage current, and a peak effective mobility of more than 2000 cm2/V·s. In addition, fabrication process uses a low overall processing temperature (≤ 400 °C) to maintain the high quality of the InGaAs/GaAs MQWs for the laser. Room temperature electrically-pumped lasers with a lasing wavelength of 1.03 µm and a linewidth of less than 1.7 nm were realized.

MoS2 Field-Effect Transistor with Sub-10 nm Channel Length.

Atomically thin molybdenum disulfide (MoS2) is an ideal semiconductor material for field-effect transistors (FETs) with sub-10 nm channel lengths. The high effective mass and large bandgap of MoS2 minimize direct source-drain tunneling, while its atomically thin body maximizes the gate modulation efficiency in ultrashort-channel transistors. However, no experimental study to date has approached the sub-10 nm scale due to the multiple challenges related to nanofabrication at this length scale and the high contact resistance traditionally observed in MoS2 transistors. Here, using the semiconducting-to-metallic phase transition of MoS2, we demonstrate sub-10 nm channel-length transistor fabrication by directed self-assembly patterning of mono- and trilayer MoS2. This is done in a 7.5 nm half-pitch periodic chain of transistors where semiconducting (2H) MoS2 channel regions are seamlessly connected to metallic-phase (1T') MoS2 access and contact regions. The resulting 7.5 nm channel-length MoS2 FET has a low off-current of 10 pA/µm, an on/off current ratio of >107, and a subthreshold swing of 120 mV/dec. The experimental results presented in this work, combined with device transport modeling, reveal the remarkable potential of 2D MoS2 for future sub-10 nm technology nodes.

Design, Modeling, and Fabrication of Chemical Vapor Deposition Grown MoS2 Circuits with E-Mode FETs for Large-Area Electronics.

Two-dimensional electronics based on single-layer (SL) MoS2 offers significant advantages for realizing large-scale flexible systems owing to its ultrathin nature, good transport properties, and stable crystalline structure. In this work, we utilize a gate first process technology for the fabrication of highly uniform enhancement mode FETs with large mobility and excellent subthreshold swing. To enable large-scale MoS2 circuit, we also develop Verilog-A compact models that accurately predict the performance of the fabricated MoS2 FETs as well as a parametrized layout cell for the FET to facilitate the design and layout process using computer-aided design (CAD) tools. Using this CAD flow, we designed combinational logic gates and sequential circuits (AND, OR, NAND, NOR, XNOR, latch, edge-triggered register) as well as switched capacitor dc-dc converter, which were then fabricated using the proposed flow showing excellent performance. The fabricated integrated circuits constitute the basis of a standard cell digital library that is crucial for electronic circuit design using hardware description languages. The proposed design flow provides a platform for the co-optimization of the device fabrication technology and circuits design for future ubiquitous flexible and transparent electronics using two-dimensional materials.

Physical fault tolerance of nanoelectronics.

The error rate in complementary transistor circuits is suppressed exponentially in electron number, arising from an intrinsic physical implementation of fault-tolerant error correction. Contrariwise, explicit assembly of gates into the most efficient known fault-tolerant architecture is characterized by a subexponential suppression of error rate with electron number, and incurs significant overhead in wiring and complexity. We conclude that it is more efficient to prevent logical errors with physical fault tolerance than to correct logical errors with fault-tolerant architecture.

Formation of single tiers of bridging silicon nanowires for transistor applications using vapor-liquid-solid growth from short silicon-on-insulator sidewalls.

Single tiers of silicon nanowires that bridge the gap between the short sidewalls of silicon-on-insulator (SOI) source/drain pads are formed. The formation of a single tier of bridging nanowires is enabled by the attachment of a single tier of Au catalyst nanoparticles to short SOI sidewalls and the subsequent growth of epitaxial nanowires via the vapor-liquid-solid (VLS) process. The growth of unobstructed nanowire material occurs due to the attachment of catalyst nanoparticles on silicon surfaces and the removal of catalyst nanoparticles from the SOI-buried oxide (BOX). Three-terminal current-voltage measurements of the structure using the substrate as a planar backgate after VLS nanowire growth reveal transistor behaviour characteristics.