Ambipolar MoTe2 transistors and their applications in logic circuits.

We report ambipolar charge transport in α-molybdenum ditelluride (MoTe2 ) flakes, whereby the temperature dependence of the electrical characteristics was systematically analyzed. The ambipolarity of the charge transport originated from the formation of Schottky barriers at the metal/MoTe2 contacts. The Schottky barrier heights as well as the current on/off ratio could be modified by modulating the electrostatic fields of the back-gate voltage (Vbg) and drain-source voltage (Vds). Using these ambipolar MoTe2 transistors we fabricated complementary inverters and amplifiers, demonstrating their feasibility for future digital and analog circuit applications.

Barrier inhomogeneities at vertically stacked graphene-based heterostructures.

The integration of graphene and other atomically flat, two-dimensional materials has attracted much interest and been materialized very recently. An in-depth understanding of transport mechanisms in such heterostructures is essential. In this study, vertically stacked graphene-based heterostructure transistors were manufactured to elucidate the mechanism of electron injection at the interface. The temperature dependence of the electrical characteristics was investigated from 300 to 90 K. In a careful analysis of current-voltage characteristics, an unusual decrease in the effective Schottky barrier height and increase in the ideality factor were observed with decreasing temperature. A model of thermionic emission with a Gaussian distribution of barriers was able to precisely interpret the conduction mechanism. Furthermore, mapping of the effective Schottky barrier height is unmasked as a function of temperature and gate voltage. The results offer significant insight for the development of future layer-integration technology based on graphene-based heterostructures.

Suppression of thermally activated carrier transport in atomically thin MoS2 on crystalline hexagonal boron nitride substrates.

We present the temperature-dependent carrier mobility of atomically thin MoS2 field-effect transistors on crystalline hexagonal boron nitride (h-BN) and SiO2 substrates. Our results reveal distinct weak temperature dependence of the MoS2 devices on h-BN substrates. The room temperature mobility enhancement and reduced interface trap density of the single and bilayer MoS2 devices on h-BN substrates further indicate that reducing substrate traps is crucial for enhancing the mobility in atomically thin MoS2 devices.

Thickness-dependent interfacial Coulomb scattering in atomically thin field-effect transistors.

Two-dimensional semiconductors are structurally ideal channel materials for the ultimate atomic electronics after silicon era. A long-standing puzzle is the low carrier mobility (µ) in them as compared with corresponding bulk structures, which constitutes the main hurdle for realizing high-performance devices. To address this issue, we perform a combined experimental and theoretical study on atomically thin MoS2 field effect transistors with varying the number of MoS2 layers (NLs). Experimentally, an intimate µ-NL relation is observed with a 10-fold degradation in µ for extremely thinned monolayer channels. To accurately describe the carrier scattering process and shed light on the origin of the thinning-induced mobility degradation, a generalized Coulomb scattering model is developed with strictly considering device configurative conditions, that is, asymmetric dielectric environments and lopsided carrier distribution. We reveal that the carrier scattering from interfacial Coulomb impurities (e.g., chemical residues, gaseous adsorbates, and surface dangling bonds) is greatly intensified in extremely thinned channels, resulting from shortened interaction distance between impurities and carriers. Such a pronounced factor may surpass lattice phonons and serve as dominant scatterers. This understanding offers new insight into the thickness induced scattering intensity, highlights the critical role of surface quality in electrical transport, and would lead to rational performance improvement strategies for future atomic electronics.

Enhanced current-rectification in bilayer graphene with an electrically tuned sloped bandgap.

We propose a novel sloped dielectric geometry in graphene as a band engineering method for widening the depletion region and increasing the electrical rectification effect in graphene pn junctions. Enhanced current-rectification was achieved in a bilayer graphene with a sloped dielectric top gate and a normal back gate. A bias was applied to the top gate to induce a spatially modulated and sloped band configuration, while a back-gate bias was applied to open a bandgap. The sloped band can be tuned to separate n- and p-type regions in the bilayer graphene, depending on a suitable choice of gate voltage. The effective depletion region between the n- and p-type regions can be spatially enlarged due to the proposed top-gate structure. As a result, a strong non-linear electric current was observed during drain bias sweeping, demonstrating the expected rectification behavior with an on/off ratio higher than all previously reported values for graphene pn junctions. The observed rectification was modified to a linear current-voltage relationship by adjusting the biases of both gates to form an nn- or pp-type junction configuration. These results demonstrate that an external voltage can control the current flow in atomic film diodes.