Bottom-up fabrication of InAs-on-nothing MOSFET using selective area molecular beam epitaxy.

In this paper we report on the fabrication and electrical characterization of InAs-on-nothing metal-oxide-semiconductor field-effect transistor composed of a suspended InAs channel and raised InAs n+ contacts. This architecture is obtained using 3D selective and localized molecular beam epitaxy on a lattice mismatched InP substrate. The suspended InAs channel and InAs n+ contacts feature a reproducible and uniform shape with well-defined 3D sidewalls. Devices with 1 µm gate length present a saturation drain current (I Dsat) of 300 mA mm-1 at V DS = 0.8 V and a trans-conductance (GM ) of 120 mS mm-1 at V DS = 0.5 V. In terms of electrostatic control, the devices display a minimal subthreshold swing of 110 mV dec-1 at V DS = 0.5 V and a small drain induced barrier lowering of 50 mV V-1.

100 nm AlSb/InAs HEMT for ultra-low-power consumption, low-noise applications.

We report on high frequency (HF) and noise performances of AlSb/InAs high electron mobility transistor (HEMT) with 100 nm gate length at room temperature in low-power regime. Extrinsic cut-off frequencies fT/f max of 100/125 GHz together with minimum noise figure NF(min) = 0.5 dB and associated gain G(ass) = 12 dB at 12 GHz have been obtained at drain bias of only 80 mV, corresponding to 4 mW/mm DC power dissipation. This demonstrates the great ability of AlSb/InAs HEMT for high-frequency operation combined with low-noise performances in ultra-low-power regime.

Gate length variation effect on performance of gate-first self-aligned In0.53Ga0.47As MOSFET.

A multi-gate n-type In0.53Ga0.47As MOSFET is fabricated using gate-first self-aligned method and air-bridge technology. The devices with different gate lengths were fabricated with the Al2O3 oxide layer with the thickness of 8 nm. In this letter, impact of gate length variation on device parameter such as threshold voltage, high and low voltage transconductance, subthreshold swing and off current are investigated at room temperature. Scaling the gate length revealed good enhancement in all investigated parameters but the negative shift in threshold voltage was observed for shorter gate lengths. The high drain current of 1.13 A/mm and maximum extrinsic transconductance of 678 mS/mm with the field effect mobility of 364 cm(2)/Vs are achieved for the gate length and width of 0.2 µm and 30 µm, respectively. The source/drain overlap length for the device is approximately extracted about 51 nm with the leakage current in order of 10(-8) A. The results of RF measurement for cut-off and maximum oscillation frequency for devices with different gate lengths are compared.

Numerical and experimental assessment of charge control in III-V nano-metal-oxide-semiconductor field-effect transistor.

III-V Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with a gate stack based on high-kappa dielectric appears as an appealing solution to increase the performance of either microwave or logic circuits with low supply voltage (V(DD)). The main objective of this work is to provide a theoretical model of the gate charge control in III-V MOS capacitors (MOSCAPs) using the accurate self-consistent solution of 1D and 2D Poisson-Schrödinger equations. This study allows us to identify the major mechanisms which must be included to get theoretical calculations in good agreement with experiments. Actually, our results obtained for an Al2O3/In0.53Ga0.47As MOSCAP structure are successfully compared to experimental measurements. We evaluate how III-V MOS technology is affected by the density of interface states which favors the Fermi level pinning at the Al2O3/In0.53Ga0.47As interface in both depletion and inversion regimes, which is a consequence of the poor gate control of the mobile inversion carrier density. The high energy valleys (satellite valleys) contribution observed in many theoretical calculations appears to be fully negligible in the presence of interface states. The enhancement of doping density in the channel is shown to improve the short-channel effect (SCE) immunity but to the price of higher sensitivity to the interface trap effect which manifests through a low Fermi level movement efficiency at interface in OFF-state and a low inversion carrier density in ON-state, even in the long channel case.