RESUMO
Among the challenges hindering the integration of carbon nanotube (CNT) transistors in digital technology are the lack of a scalable self-aligned gate and complementary n- and p-type devices. We report CNT transistors with self-aligned gates scaled down to 20 nm in the ideal gate-all-around geometry. Uniformity of the gate wrapping the nanotube channels is confirmed, and the process is shown not to damage the CNTs. Further, both n- and p-type transistors were realized by using the appropriate gate dielectric-HfO2 yielded n-type and Al2O3 yielded p-type-with quantum simulations used to explore the impact of important device parameters on performance. These discoveries not only provide a promising platform for further research into gate-all-around CNT devices but also demonstrate that scalable digital switches with realistic technological potential can be achieved with carbon nanotubes.
RESUMO
Although carbon nanotube (CNT) transistors have been promoted for years as a replacement for silicon technology, there is limited theoretical work and no experimental reports on how nanotubes will perform at sub-10 nm channel lengths. In this manuscript, we demonstrate the first sub-10 nm CNT transistor, which is shown to outperform the best competing silicon devices with more than four times the diameter-normalized current density (2.41 mA/µm) at a low operating voltage of 0.5 V. The nanotube transistor exhibits an impressively small inverse subthreshold slope of 94 mV/decade-nearly half of the value expected from a previous theoretical study. Numerical simulations show the critical role of the metal-CNT contacts in determining the performance of sub-10 nm channel length transistors, signifying the need for more accurate theoretical modeling of transport between the metal and nanotube. The superior low-voltage performance of the sub-10 nm CNT transistor proves the viability of nanotubes for consideration in future aggressively scaled transistor technologies.
