RESUMO
We directly demonstrate the importance of buffer elimination at the graphene/SiC(0001) interface for high frequency applications. Upon successful buffer elimination, carrier mobility increases from an average of 800 cm(2)/(V s) to >2000 cm(2)/(V s). Additionally, graphene transistor current saturation increases from 750 to >1300 mA/mm, and transconductance improves from 175 mS/mm to >400 mS. Finally, we report a 10× improvement in the extrinsic current gain response of graphene transistors with optimal extrinsic current-gain cutoff frequencies of 24 GHz.
RESUMO
A promising route for the synthesis of large-area graphene, suitable for standard device fabrication techniques, is the sublimation of silicon from silicon carbide at elevated temperatures (>1200 degrees C). Previous reports suggest that graphene nucleates along the (110n) plane, known as terrace step edges, on the silicon carbide surface. However, to date, a fundamental understanding of the nucleation of graphene on silicon carbide is lacking. We provide the first direct evidence that nucleation of epitaxial graphene on silicon carbide occurs along the (110n) plane and show that the nucleated graphene quality improves as the synthesis temperature is increased. Additionally, we find that graphene on the (110n) plane can be significantly thicker than its (0001) counterpart and appears not to have a thickness limit. Finally, we find that graphene along the (110n) plane can contain a high density of structural defects, often the result of the underlying substrate, which will undoubtedly degrade the electronic properties of the material. Addressing the presence of non-uniform graphene that may contain structural defects at terrace step edges will be key to the development of a large-scale graphene technology derived from silicon carbide.
