Two-Dimensional Cold Electron Transport for Steep-Slope Transistors.

Room-temperature Fermi-Dirac electron thermal excitation in conventional three-dimensional (3D) or two-dimensional (2D) semiconductors generates hot electrons with a relatively long thermal tail in energy distribution. These hot electrons set a fundamental obstacle known as the "Boltzmann tyranny" that limits the subthreshold swing (SS) and therefore the minimum power consumption of 3D and 2D field-effect transistors (FETs). Here, we investigated a graphene (Gr)-enabled cold electron injection where the Gr acts as the Dirac source to provide the cold electrons with a localized electron density distribution and a short thermal tail at room temperature. These cold electrons correspond to an electronic refrigeration effect with an effective electron temperature of ∼145 K in the monolayer MoS2, which enables the transport factor lowering and thus the steep-slope switching (across for three decades with a minimum SS of 29 mV/decade at room temperature) for a monolayer MoS2 FET. Especially, a record-high sub-60-mV/decade current density (over 1 µA/µm) can be achieved compared to conventional steep-slope technologies such as tunneling FETs or negative capacitance FETs using 2D or 3D channel materials. Our work demonstrates the potential of a 2D Dirac-source cold electron transistor as a steep-slope transistor concept for future energy-efficient nanoelectronics.

Diode-Like Selective Enhancement of Carrier Transport through Metal-Semiconductor Interface Decorated by Monolayer Boron Nitride.

2D semiconductors such as monolayer molybdenum disulfide (MoS2 ) are promising material candidates for next-generation nanoelectronics. However, there are fundamental challenges related to their metal-semiconductor (MS) contacts, which limit the performance potential for practical device applications. In this work, 2D monolayer hexagonal boron nitride (h-BN) is exploited as an ultrathin decorating layer to form a metal-insulator-semiconductor (MIS) contact, and an innovative device architecture is designed as a platform to reveal a novel diode-like selective enhancement of the carrier transport through the MIS contact. The contact resistance is significantly reduced when the electrons are transported from the semiconductor to the metal, but is barely affected when the electrons are transported oppositely. A concept of carrier collection barrier is proposed to interpret this intriguing phenomenon as well as a negative Schottky barrier height obtained from temperature-dependent measurements, and the critical role of the collection barrier at the drain end is shown for the overall transistor performance.