Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem.

OBJECTIVE: To develop and verify a CMOS bone-guided cochlear implant (BGCI) microsystem with electrodes placed on the bone surface of the cochlea and the outside of round window for treating high-frequency hearing loss. METHODS: The BGCI microsystem consists of an external unit and an implanted unit. The external system-on-chip is designed to process acoustic signals through an acquisition circuit and an acoustic DSP processor to generate stimulation patterns and commands that are transmitted to the implanted unit through a 13.56 MHz wireless power and bidirectional data telemetry. In the wireless power telemetry, a voltage doubler/tripler (2X/3X) active rectifier is used to enhance the power conversion efficiency and generate 2 and 3 V output voltages. In the wireless data telemetry, phase-locked loop based binary phase-shift keying and load-shift keying modulators/demodulators are adopted for the downlink and uplink data through high-Q coils, respectively. The implanted chip with four-channel high-voltage-tolerant stimulator generates biphasic stimulation currents up to 800 µA. RESULTS: Electrical tests on the fabricated BGCI microsystem have been performed to verify the chip functions. The in vivo animal tests in guinea pigs have shown the evoked third wave of electrically evoked auditory brainstem response waveforms. It is verified that auditory nerves can be successfully stimulated and acoustic hearing can be partially preserved. CONCLUSION AND SIGNIFICANCE: Different from traditional cochlear implants, the proposed BGCI microsystem is less invasive, preserves partially acoustic hearing, and provides an effective alternative for treating high-frequency hearing loss.

A Digitally Dynamic Power Supply Technique for 16-Channel 12 V-Tolerant Stimulator Realized in a 0.18- µm 1.8-V/3.3-V Low-Voltage CMOS Process.

A new digitally dynamic power supply technique for 16-channel 12-V-tolerant stimulator is proposed and realized in a 0.18-µm 1.8-V/3.3-V CMOS process. The proposed stimulator uses four stacked transistors as the pull-down switch and pull-up switch to withstand 4 times the nominal supply voltage (4 × V DD). With the dc input voltage of 3.3 V, the regulated three-stage charge pump, which is capable of providing 11.3-V voltage at 3-mA loading current, achieves dc conversion efficiency of up to 69% with 400-pF integrated capacitance. Power consumption is reduced by implementing the regulated charge pump to provide a dynamic dc output voltage with a 0.5-V step. The proposed digitally dynamic power supply technique, which is implemented by using a p-type metal oxide semiconductor (PMOS) inverter with pull-down current source and digital controller, greatly improves the power efficiency of a system. The silicon area of the stimulator is approximately 3.5 mm2 for a 16-channel implementation. The functionalities of the proposed stimulator have been successfully verified through animal test.