Room-Temperature Fabricated Multilevel Nonvolatile Lead-Free Cesium Halide Memristors for Reconfigurable In-Memory Computing.

Recently, conductive-bridging memristors based on metal halides, such as halide perovskites, have been demonstrated as promising components for brain-inspired hardware-based neuromorphic computing. However, realizing devices that simultaneously fulfill all of the key merits (low operating voltage, high dynamic range, multilevel nonvolatile storage capability, and good endurance) remains a great challenge. Herein, we describe lead-free cesium halide memristors incorporating a MoOX interfacial layer as a type of conductive-bridging memristor. With this design, we obtained highly uniform and reproducible memristors that exhibited all-around resistive switching characteristics: ultralow operating voltages (<0.18 V), low variations (<30 mV), long retention times (>106 s), high endurance (>105, full on/off cycles), record-high on/off ratios (>1010, smaller devices having areas <5 × 10-4 mm2), fast switching (<200 ns), and multilevel programming abilities (>64 states). With these memristors, we successfully implemented stateful logic functions in a reconfigurable architecture and accomplished a high classification accuracy (ca. 90%) in the simulated hand-written-digits classification task, suggesting their versatility in future in-memory computing applications. In addition, we exploited the room-temperature fabrication of the devices to construct a fully functional three-dimensional stack of memristors, which demonstrates their potential of high-density integration desired for data-intensive neuromorphic computing. High-performance, environmentally friendly cesium halide memristors provide opportunities toward next-generation electronics beyond von Neumann architectures.

All-Vacuum-Deposited Perovskite X-ray Detector with a Record-High Self-Powered Sensitivity of 1.2 C Gy-1 cm-3.

Highly sensitive X-ray detection is crucial in, for example, medical imaging and secure inspection. Halide perovskite X-ray detectors are promising candidates for detecting highly energetic radiation. In this report, we describe vacuum-deposited Cs-based perovskite X-ray detectors possessing a p-i-n architecture. Because of the built-in potential of the p-i-n structure, these perovskite X-ray detectors were capable of efficient charge collection and displayed an exceptionally high X-ray sensitivity (1.2 C Gyair-1 cm-3) under self-powered, zero-bias conditions. We ascribe the outstanding X-ray sensitivity of the vacuum-deposited CsPbI2Br devices to their prominent charge carrier mobility. Moreover, these devices functioned with a lowest detection limit of 25.69 nGyair s-1 and possessed excellent stability after exposure to over 3000 times the total dose of a chest X-ray image. For comparison, we also prepared traditional spin-coated CH3NH3-based perovskite devices having a similar device architecture. Their volume sensitivity was only one-fifth of that of the vacuum-deposited CsPbI2Br devices. Thus, all-vacuum deposition appears to be a new strategy for developing perovskite X-ray detectors; with a high practical deposition rate, a balance can be reached between the thickness of the absorbing layer and the fabrication time.

Reconfigurable Architecture and Dataflow for Memory Traffic Minimization of CNNs Computation.

Computation of convolutional neural network (CNN) requires a significant amount of memory access, which leads to lots of energy consumption. As the increase of neural network scale, this phenomenon is further obvious, the energy consumption of memory access and data migration between on-chip buffer and off-chip DRAM is even much more than the computation energy on processing element array (PE array). In order to reduce the energy consumption of memory access, a better dataflow to maximize data reuse and minimize data migration between on-chip buffer and external DRAM is important. Especially, the dimension of input feature map (ifmap) and filter weight are much different for each layer of the neural network. Hardware resources may not be effectively utilized if the array architecture and dataflow cannot be reconfigured layer by layer according to their ifmap dimension and filter dimension, and result in a large quantity of data migration on certain layers. However, a thorough exploration of all possible configurations is time consuming and meaningless. In this paper, we propose a quick and efficient methodology to adapt the configuration of PE array architecture, buffer assignment, dataflow and reuse methodology layer by layer with the given CNN architecture and hardware resource. In addition, we make an exploration on the different combinations of configuration issues to investigate their effectiveness and can be used as a guide to speed up the thorough exploration process.

Retention-Aware DRAM Auto-Refresh Scheme for Energy and Performance Efficiency.

Dynamic random access memory (DRAM) circuits require periodic refresh operations to prevent data loss. As DRAM density increases, DRAM refresh overhead is even worse due to the increase of the refresh cycle time. However, because of few the cells in memory that have lower retention time, DRAM has to raise the refresh frequency to keep the data integrity, and hence produce unnecessary refreshes for the other normal cells, which results in a large refresh energy and performance delay of memory access. In this paper, we propose an integration scheme for DRAM refresh based on the retention-aware auto-refresh (RAAR) method and 2x granularity auto-refresh simultaneously. We also explain the corresponding modification need on memory controllers to support the proposed integration refresh scheme. With the given profile of weak cells distribution in memory banks, our integration scheme can choose the most appropriate refresh technique in each refresh time. Experimental results on different refresh cycle times show that the retention-aware refresh scheme can properly improve the system performance and have a great reduction in refresh energy. Especially when the number of weak cells increased due to the thermal effect of 3D-stacked architecture, our methodology still keeps the same performance and energy efficiency.