Comparison of CoW/SiO2 and CoB/SiO2 Interconnects from the Perspective of Electrical and Reliability Characteristics.

As the feature size of integrated circuits has been scaled down to 10 nm, the rapid increase in the electrical resistance of copper (Cu) metallization has become a critical issue. To alleviate the resistance increases of Cu lines, co-sputtered CoW and CoB alloying metals were investigated as conductors and barriers in this study. Annealing CoM (M = W or B)/SiO2/p-Si structures reduced the resistivity of CoM alloys, removed sputtering-deposition-induced damage, and promoted adhesion. Additionally, both annealed CoW/SiO2 or CoB/SiO2 structures displayed a negligible Vfb shift from capacitance-voltage measurements under electrical stress, revealing an effective barrier capacity, which is attributed to the formation of MOx layers at the CoM/SiO2 interface. Based on the thermodynamics, the B2O3 layer tends to form more easily than the WOx layer. Hence, the annealed CoB/SiO2/p-Si MIS capacitor had a higher capacitance and a larger breakdown strength did than the annealed CoW/SiO2/p-Si MIS capacitor.

Reliability Characteristics of Metal-Insulator-Semiconductor Capacitors with Low-Dielectric-Constant Materials.

In this study, the reliability characteristics of metal-insulator-semiconductor (MIS) capacitor structures with low-dielectric-constant (low-k) materials have been investigated in terms of metal gate area and geometry and thickness of dielectric film effects. Two low-k materials, dense and porous low-k films, were used. Experimental results indicated that the porous low-k films had shorter breakdown times, lower Weibull slope parameters and electric field acceleration factors, and weaker thickness-dependence breakdowns compared to the dense low-k films. Additionally, a larger derivation in dielectric breakdown projection model and a single Weilbull plot of the breakdown time distributions from various areas merging was observed. This study also pointed out that the porous low-k film in the irregular-shaped metal gate MIS capacitor had a larger dielectric breakdown time than that in the square- and circle-shaped samples, which violates the trend of the sustained electric field. As a result, another breakdown mechanism exists in the irregular-shaped sample, which is required to explore in the future work.

Chemical-Structure Evolution Model for the Self-Assembling of Amine-Terminated Monolayers on Nanoporous Carbon-Doped Organosilicate in Tightly Controlled Environments.

Amine-terminated self-assembled monolayers are molecular nanolayers, typically formed via wet-chemical solution on specific substrates for precision surface engineering or interface modification. However, homogeneous assembling of a highly ordered monolayer by the facile, wet method is rather tricky because it involves process parameters, such as solvent type, molecular concentration, soaking time and temperature, and humidity level. Here, we select 3-aminopropyltrimethoxysilane (APTMS) as a model molecule of aminosilane for the silanization of nanoporous carbon-doped organosilicate (p-SiOCH) under tightly controlled process environments. Surface mean roughness (Ra) and the water contact angle (θ) of the p-SiOCH layers upon silanization at a 10% humidity-controlled environment behave similarly and follow a three-stage evolution: a leap to a maximum at 15 min for Ra (from 0.227 to 0.411 nm) and θ (from 25 to 86°), followed by a gradual decrease to 0.225 nm and 69o, finally leveling off at the above values (>60 min). The -NH3+ fraction indicating monolayer disorientation evolves in a similar fashion. The fully grown monolayer is highly oriented yielding an unprecedented low -NH3+ fraction of 0.08 (and 0.92 of upright -NH2 groups). However, while having a similar thickness of approximately 1.4 ± 0.1 nm, the molecular layers grown at 30% relative humidity exhibit a significantly elevated -NH3+ fraction of 0.42, indicating that controlling the humidity is vital to the fabrication of highly oriented APTMS molecular layers. A bonding-structure evolution model, as distinct from those offered previously, is proposed and discussed.

Electrical Characteristics and Reliability of Nitrogen-Stuffed Porous Low-k SiOCH/Mn2O3-xN/Cu Integration.

In our previous study, a novel barrier processing on a porous low-dielectric constant (low-k) film was developed: an ultrathin Mn oxide on a nitrogen-stuffed porous carbon-doped organosilica film (p-SiOCH(N)) as a barrier of the Cu film was fabricated. To form a better barrier Mn2O3-xN film, additional annealing at 450 °C was implemented. In this study, the electrical characteristics and reliability of this integrated Cu/Mn2O3-xN/p-SiOCH(N)/Si structure were investigated. The proposed Cu/Mn2O3-xN/p-SiOCH(N)/Si capacitors exhibited poor dielectric breakdown characteristics in the as-fabricated stage, although, less degradation was found after thermal stress. Moreover, its time-dependence-dielectric-breakdown electric-field acceleration factor slightly increased after thermal stress, leading to a larger dielectric lifetime in a low electric-field as compared to other metal-insulator-silicon (MIS) capacitors. Furthermore, its Cu barrier ability under electrical or thermal stress was improved. As a consequence, the proposed Cu/Mn2O3-xN/p-SiCOH(N) scheme is promising integrity for back-end-of-line interconnects.

Effect of interfacial condition on electromigration for narrow and wide copper interconnects.

The sub-micron damascene interconnects, electromigration is mainly due to the diffusion at the interfaces of Cu with liner or dielectric capping layer. Many reports have shown that Cu/capping dielectric is the dominant interface. Experiments were performed to study the effect of the interfacial conditions of Cu/capping dielectric material on electromigration for narrow and wide Cu lines. The results revealed significant differences in electromigration behavior of via-fed upper and lower layer damascene test structures. For upper layer test structure, the capping layer and plasma surface treatment significantly dominated EM performance for different line width structures. In the case of lower layer test structure, the electromigration time to failure was found to be influenced by the capping layer and via process, and it remained unaffected by the plasma surface treatment for the narrow Cu line. For the wide line width (3X), electromigration performance was influenced by the current crowding on via-bottom.