Boron Triiodide-Mediated Reduction of Nitroarenes Using Borohydride Reagents.

The reduction of nitroarenes using KBH4 and I2 is described. BI3 is generated in situ and was shown to be the active reductant. Conditions were optimized for BI3 generation and then applied to a wide range of nitroarenes, including traditionally challenging substrates. The method constitutes a practical reduction option which produces low-toxicity boric acid and potassium iodide upon workup.

Impact of Nitridation on Bias Temperature Instability and Hard Breakdown Characteristics of SiON MOSFETs.

We study how nitridation, applied to SiON gate layers, impacts the reliability of planar metal-oxide-semiconductor field effect transistors (MOSFETs) subjected to negative and positive bias temperature instability (N/PBTI) as well as hard breakdown (HBD) characteristics of these devices. Experimental data demonstrate that p-channel transistors with SiON layers characterized by a higher nitrogen concentration have poorer NBTI reliability compared to their counterparts with a lower nitrogen content, while PBTI in n-channel devices is negligibly weak in all samples independently of the nitrogen concentration. The Weibull distribution of HBD fields extracted from experimental data in devices with a higher N density are shifted towards lower values with respect to that measured in MOSFETs, and SiON films have a lower nitrogen concentration. Based on these findings, we conclude that a higher nitrogen concentration results in the aggravation of BTI robustness and HBD characteristics.

Sidewall crystalline orientation effect of post-treatments for a replacement metal gate bulk fin field effect transistor.

The crystalline orientation effect is investigated for post-treatments of a replacement metal gate (RMG) p-type bulk fin field effect transistor (FinFET). After post-deposition annealing (PDA) and SF6 plasma treatment, the hole mobility is improved. From low-frequency noise analysis, reduction of the trap density and noise level is observed in PDA- and SF6-plasma-treated devices. (100) sidewall-oriented FinFETs show a lower noise level because of fewer interface traps compared to (110) sidewall-oriented devices. SF6 plasma affects the interface traps, whereas PDA relatively more affects bulk oxide traps for RMG high-k last FinFET.