High-Performance Indium-Based Oxide Transistors with Multiple Channels Through Nanolaminate Structure Fabricated by Plasma-Enhanced Atomic Layer Deposition.

An atomic-layer-deposited oxide nanolaminate (NL) structure with 3 dyads where a single dyad consists of a 2-nm-thick confinement layer (CL) (In0.84Ga0.16O or In0.75Zn0.25O), and a barrier layer (BL) (Ga2O3) was designed to obtain superior electrical performance in thin-film transistors (TFTs). Within the oxide NL structure, multiple-channel formation was demonstrated by a pile-up of free charge carriers near CL/BL heterointerfaces in the form of the so-called quasi-two-dimensional electron gas (q2DEG), which leads to an outstanding carrier mobility (µFE) with band-like transport, steep gate swing (SS), and positive threshold voltage (VTH) behavior. Furthermore, reduced trap densities in oxide NL compared to those of conventional oxide single-layer TFTs ensures excellent stabilities. The optimized device with the In0.75Zn0.25O/Ga2O3 NL TFT showed remarkable electrical performance: µFE of 77.1 ± 0.67 cm2/(V s), VTH of 0.70 ± 0.25 V, SS of 100 ± 10 mV/dec, and ION/OFF of 8.9 × 109 with a low operation voltage range of ≤2 V and excellent stabilities (ΔVTH of +0.27, -0.55, and +0.04 V for PBTS, NBIS, and CCS, respectively). Based on in-depth analyses, the enhanced electrical performance is attributed to the presence of q2DEG formed at carefully engineered CL/BL heterointerfaces. Technological computer-aided design (TCAD) simulation was performed theoretically to confirm the formation of multiple channels in an oxide NL structure where the formation of a q2DEG was verified in the vicinity of CL/BL heterointerfaces. These results clearly demonstrate that introducing a heterojunction or NL structure concept into this atomic layer deposition (ALD)-derived oxide semiconductor system is a very effective strategy to boost the carrier-transporting properties and improve the photobias stability in the resulting TFTs.

Comparative Study of Atomic Layer Deposited Indium-Based Oxide Transistors with a Fermi Energy Level-Engineered Heterojunction Structure Channel through a Cation Combinatorial Approach.

Amorphous indium-gallium-zinc oxide (a-IGZO) has become a standard channel ingredient of switching/driving transistors in active-matrix organic light-emitting diode (AMOLED) televisions. However, mobile AMOLED displays with a high pixel density (≥500 pixels per inch) and good form factor do not often employ a-IGZO transistors due to their modest mobility (10-20 cm2/(V s)). Hybrid low-temperature polycrystalline silicon and oxide transistor (LTPO) technology is being adapted in high-end mobile AMOLED devices due to its ultralow power consumption and excellent current drivability. The critical issues of LTPO (including a complicated structure and high fabrication costs) require a search for alternative all-oxide thin-film transistors (TFTs) with low-cost processability and simple device architecture. The atomic layer deposition (ALD) method is a promising route for high-performance all-oxide TFTs due to its unique features, such as in situ cation composition tailoring ability, precise nanoscale thickness controllability, and excellent step coverage. Here, we report an in-depth comparative investigation of TFTs with indium-gallium oxide (IGO)/gallium-zinc oxide (GZO) and indium-zinc oxide (IZO)/GZO heterojunction stacks using an ALD method. IGO and IZO layers with different compositions were tested as a confinement layer (CL), whereas the GZO layer was used as a barrier layer (BL). Optimal IGO/GZO and IZO/GZO channels were carefully designed on the basis of their energy band properties, where the formation of a quasi-two-dimensional electron gas (q2DEG) near the CL/BL interface is realized by rational design of the band gaps and work-functions of the IGO, IZO, and GZO thin films. To verify the effect of q2DEG formation, the device performances and stabilities of TFTs with CL/BL oxide heterojunction stacks were examined and compared to those of TFTs with a single CL layer. The optimized device with the In0.75Zn0.25O/Ga0.80Zn0.20O stack showed remarkable electrical performance: µFE of 76.7 ± 0.51 cm2/(V s), VTH of -0.37 ± 0.19 V, SS of 0.13 ± 0.01 V/dec, and ION/OFF of 2.5 × 1010 with low operation voltage range of ≥2 V and excellent stabilities (ΔVTH of +0.35, -0.67, and +0.08 V for PBTS, NBIS, and CCS, respectively). This study suggests the feasibility of using high-performance ALD-derived oxide TFTs (which can compete with the performance of LTPO transistors) for high-end mobile AMOLED displays.

Achieving a Low-Voltage, High-Mobility IGZO Transistor through an ALD-Derived Bilayer Channel and a Hafnia-Based Gate Dielectric Stack.

Ultrahigh-resolution displays for augmented reality (AR) and virtual reality (VR) applications require a novel architecture and process. Atomic-layer deposition (ALD) enables the facile fabrication of indium-gallium zinc oxide (IGZO) thin-film transistors (TFTs) on a substrate with a nonplanar surface due to its excellent step coverage and accurate thickness control. Here, we report all-ALD-derived TFTs using IGZO and HfO2 as the channel layer and gate insulator, respectively. A bilayer IGZO channel structure consisting of a 10 nm base layer (In0.52Ga0.29Zn0.19O) with good stability and a 3 nm boost layer (In0.82Ga0.08Zn0.10O) with extremely high mobility was designed based on a cation combinatorial study of the ALD-derived IGZO system. Reducing the thickness of the HfO2 dielectric film by the ALD process offers high areal capacitance in field-effect transistors, which allows low-voltage drivability and enhanced carrier transport. The intrinsic inferior stability of the HfO2 gate insulator was effectively mitigated by the insertion of an ALD-derived 4 nm Al2O3 interfacial layer between HfO2 and the IGZO film. The optimized bilayer IGZO TFTs with HfO2-based gate insulators exhibited excellent performances with a high field-effect mobility of 74.0 ± 0.91 cm2/(V s), a low subthreshold swing of 0.13 ± 0.01 V/dec, a threshold voltage of 0.20 ± 0.24 V, and an ION/OFF of ∼3.2 × 108 in a low-operation-voltage (≤2 V) range. This promising result was due to the synergic effects of a bilayer IGZO channel and HfO2-based gate insulator with a high permittivity, which were mainly attributed to the effective carrier confinement in the boost layer with high mobility, low free carrier density of the base layer with a low VO concentration, and HfO2-induced high effective capacitance.

High-Performance Thin-Film Transistors with an Atomic-Layer-Deposited Indium Gallium Oxide Channel: A Cation Combinatorial Approach.

The effect of gallium (Ga) concentration on the structural evolution of atomic-layer-deposited indium gallium oxide (IGO) (In1-xGaxO) films as high-mobility n-channel semiconducting layers was investigated. Different Ga concentrations in 10-13 nm thick In1-xGaxO films allowed versatile phase structures to be amorphous, highly ordered, and randomly oriented crystalline by thermal annealing at either 400 or 700 °C for 1 h. Heavy Ga concentrations above 34 atom % caused a phase transformation from a polycrystalline bixbyite to an amorphous IGO film at 400 °C, while proper Ga concentration produced a highly ordered bixbyite crystal structure at 700 °C. The resulting highly ordered In0.66Ga0.34O film show unexpectedly high carrier mobility (µFE) values of 60.7 ± 1.0 cm2 V-1 s-1, a threshold voltage (VTH) of -0.80 ± 0.05 V, and an ION/OFF ratio of 5.1 × 109 in field-effect transistors (FETs). In contrast, the FETs having polycrystalline In1-xGaxO films with higher In fractions (x = 0.18 and 0.25) showed reasonable µFE values of 40.3 ± 1.6 and 31.5 ± 2.4 cm2 V-1 s-1, VTH of -0.64 ± 0.40 and -0.43 ± 0.06 V, and ION/OFF ratios of 2.5 × 109 and 1.4 × 109, respectively. The resulting superior performance of the In0.66Ga0.34O-film-based FET was attributed to a morphology having fewer grain boundaries, with higher mass densification and lower oxygen vacancy defect density of the bixbyite crystallites. Also, the In0.66Ga0.34O transistor was found to show the most stable behavior against an external gate bias stress.

Atomic Layer Deposition Process-Enabled Carrier Mobility Boosting in Field-Effect Transistors through a Nanoscale ZnO/IGO Heterojunction.

Low-temperature (≤400 °C), stackable oxide semiconductors are promising as an upper transistor ingredient for monolithic three-dimensional integration. The atomic layer deposition (ALD) route provides a low-defect, high-quality semiconducting oxide channel layer and enables accurate controllability of the chemical composition and physical thickness as well as excellent step coverage on nanoscale trench structures. Here, we report a high-mobility heterojunction transistor in a ternary indium gallium zinc oxide system using the ALD technique. The heterojunction channel structure consists of a 10 nm thick indium gallium oxide (IGO) layer as an effective transporting layer and a 3 nm thick, wide band gap ZnO layer. The formation of a two-dimensional electron gas was suggested by controlling the band gap of the IGO quantum well through In/Ga ratio tailoring and reducing the physical thickness of the ZnO film. A field-effect transistor (FET) with a ZnO/In0.83Ga0.17O1.5 heterojunction channel exhibited the highest field-effect mobility of 63.2 ± 0.26 cm2/V s, a low subthreshold gate swing of 0.26 ± 0.03 V/dec, a threshold voltage of -0.84 ± 0.85 V, and an ION/OFF ratio of 9 × 108. This surpasses the performance (carrier mobility of ∼41.7 ± 1.43 cm2/V s) of an FET with a single In0.83Ga0.17O1.5 channel. Furthermore, the gate bias stressing test results indicate that FETs with a ZnO/In1-xGaxO1.5 (x = 0.25 and 0.17) heterojunction channel are much more stable than those with a single In1-xGaxO1.5 (x = 0.35, 0.25, and 0.17) channel. Relevant discussion is given in detail on the basis of chemical characterization and technological computer-aided design simulation.