Extending High-Level Synthesis for Task-Parallel Programs.

C/C++/OpenCL-based high-level synthesis (HLS) becomes more and more popular for field-programmable gate array (FPGA) accelerators in many application domains in recent years, thanks to its competitive quality of results (QoR) and short development cycles compared with the traditional register-transfer level design approach. Yet, limited by the sequential C semantics, it remains challenging to adopt the same highly productive high-level programming approach in many other application domains, where coarse-grained tasks run in parallel and communicate with each other at a fine-grained level. While current HLS tools do support task-parallel programs, the productivity is greatly limited ① in the code development cycle due to the poor programmability, ② in the correctness verification cycle due to restricted software simulation, and ③ in the QoR tuning cycle due to slow code generation. Such limited productivity often defeats the purpose of HLS and hinder programmers from adopting HLS for task-parallel FPGA accelerators. In this paper, we extend the HLS C++ language and present a fully automated framework with programmer-friendly interfaces, unconstrained software simulation, and fast hierarchical code generation to overcome these limitations and demonstrate how task-parallel programs can be productively supported in HLS. Experimental results based on a wide range of real-world task-parallel programs show that, on average, the lines of kernel and host code are reduced by 22% and 51%, respectively, which considerably improves the programmability. The correctness verification and the iterative QoR tuning cycles are both greatly shortened by 3.2× and 6.8×, respectively. Our work is open-source at https://github.com/UCLA-VAST/tapa/.

HBM Connect: High-Performance HLS Interconnect for FPGA HBM.

With the recent release of High Bandwidth Memory (HBM) based FPGA boards, developers can now exploit unprecedented external memory bandwidth. This allows more memory-bounded applications to benefit from FPGA acceleration. However, fully utilizing the available bandwidth may not be an easy task. If an application requires multiple processing elements to access multiple HBM channels, we observed a significant drop in the effective bandwidth. The existing high-level synthesis (HLS) programming environment had limitation in producing an efficient communication architecture. In order to solve this problem, we propose HBM Connect, a high-performance customized interconnect for FPGA HBM board. Novel HLS-based optimization techniques are introduced to increase the throughput of AXI bus masters and switching elements. We also present a high-performance customized crossbar that may replace the built-in crossbar. The effectiveness of HBM Connect is demonstrated using Xilinx's Alveo U280 HBM board. Based on bucket sort and merge sort case studies, we explore several design spaces and find the design point with the best resource-performance trade-off. The result shows that HBM Connect improves the resource-performance metrics by 6.5X-211X.

Gate-tuned conductance of graphene-ribbon junctions with nanoscale width variations.

To utilize graphene as interconnection electrodes in high-density nanoelectronic structures, the electrical stability of graphene should be guaranteed under nanometer-scale deviations. Graphene-ribbon (GR) junctions with accessible dimensions (i.e., sub-micrometer widths) are used in diverse interconnection electrode applications and should be characterized properly if they are to be applied in high-density nanoelectronics. Analyzing the effects of nanoscale GR width variations on the conductance of the entire graphene electrode is necessary for their proper characterization. Here, we diagnose the conductance and thermal effect of graphene electrode junctions constructed from GRs of various widths and directions under gate-tuned voltages. On applying partial gate voltages, we identify the effect of local potential variance on the entire graphene electrode junction. As a result, we were able to perceive precise and minute conductance variations for the entire graphene electrode, arising mainly from different sub-micrometer-scale widths of the GRs, which could not be distinguished using conventional global gating methods.

Gas molecule sensing of van der Waals tunnel field effect transistors.

van der Waals (vdW) heterostructures with two-dimensional (2D) crystals such as graphene, hexagonal boron nitride (hBN) and transition metal dichalcogenides (TMDCs) allow us to demonstrate atomically thin field-effect transistors (FETs), photodetectors (PDs) and photovoltaic devices capable of higher performance and greater stability levels than conventional devices. Although there have been studies of gas molecule sensing with 2D crystal channels, vdW heterostructures based on 2D crystals have not been employed thus far. Here, utilizing graphene/WS2/graphene (G/WS2/G) vdW heterostructure tunnel FETs, we demonstrate the rectification behavior of the sensitivity signal by tuning the WS2 potential barriers as a function of the gas molecule concentration and devise a fingerprint map of the sensitivity variation corresponding to an individual ratio of two different molecules in a gas mixture. Because the separation of different gas molecule concentrations from gas mixtures is in high demand in the gas-sensing research field, this result will greatly assist in the progress on selective gas sensing.

Acceleration of EM-Based 3D CT Reconstruction Using FPGA.

Reducing radiation doses is one of the key concerns in computed tomography (CT) based 3D reconstruction. Although iterative methods such as the expectation maximization (EM) algorithm can be used to address this issue, applying this algorithm to practice is difficult due to the long execution time. Our goal is to decrease this long execution time to an order of a few minutes, so that low-dose 3D reconstruction can be performed even in time-critical events. In this paper we introduce a novel parallel scheme that takes advantage of numerous block RAMs on field-programmable gate arrays (FPGAs). Also, an external memory bandwidth reduction strategy is presented to reuse both the sinogram and the voxel intensity. Moreover, a customized processing engine based on the FPGA is presented to increase overall throughput while reducing the logic consumption. Finally, a hardware and software flow is proposed to quickly construct a design for various CT machines. The complete reconstruction system is implemented on an FPGA-based server-class node. Experiments on actual patient data show that a 26.9 × speedup can be achieved over a 16-thread multicore CPU implementation.

Two polymorphisms of interleukin-4 gene in Korean adult periodontitis.

Adult periodontitis is a multifactoral disease characterized by multiple genetic and environmental factors. In view of the importance of interleukin-4 (IL-4) gene as a genetic factor for adult periodontitis, we investigated the relationship between two polymorphisms (-590 C --> T polymorphism and 70 bp repeat polymorphism) of the human IL-4 gene and adult periodontitis in the Korean population. Genomic DNA was extracted from white blood cells of 32 adult periodontitis patients and 150 normal controls, respectively. There were no significant differences in the allele, genotype and haplotype distributions of two polymorphisms between normal controls and adult periodontitis group. Therefore, our results suggest that IL-4 gene locus contributes little to the interindividual susceptibility for adult periodontitis in Korean population.