First realization of the piezoelectronic stress-based transduction device.

We present the first realization of a monolithically integrated piezoelectronic transistor (PET), a new transduction-based computer switch which could potentially operate conventional computer logic at 1/50 the power requirements of current Si-based transistors (Chen 2014 Proc. IEEE ICICDT pp 1-4; Mamaluy et al 2014 Proc. IWCE pp 1-2). In PET operation, an input gate voltage expands a piezoelectric element (PE), transducing the input into a pressure pulse which compresses a piezoresistive element (PR). The PR resistance goes down, transducing the signal back to voltage and turning the switch 'on'. This transduction physics, in principle, allows fast, low-voltage operation. In this work, we address the processing challenges of integrating chemically incompatible PR and PE materials together within a surrounding cage against which the PR can be compressed. This proof-of-concept demonstration of a fully integrated, stand-alone PET device is a key step in the development path toward a fast, low-power very large scale integration technology.

Au stabilization and coverage of sawtooth facets on Si nanowires grown by vapor-liquid-solid epitaxy.

Si nanowires grown in UHV by Au-catalyzed vapor-liquid-solid epitaxy are known to exhibit sidewalls with {112}-type orientation that show faceting. To understand the origin of the faceting, Au induced faceting on Si(112) surfaces was studied in situ by spot-profile-analyzing low-energy electron diffraction. With increasing Au coverage at 750 degrees C, the Si(112) surface undergoes various morphological transformations until, at a critical Au coverage of about 3.1 x 10 (14) atoms/cm (2), a phase consisting of large (111) and (113) facets forms, similar in structure to the nanowire sidewalls. This phase is stable at larger Au coverages in equilibrium with Au droplets. We suggest that Si nanowire surfaces exhibit this structure, and we derive the Au coverage on the two types of facets.

High-mobility ultrathin semiconducting films prepared by spin coating.

The ability to deposit and tailor reliable semiconducting films (with a particular recent emphasis on ultrathin systems) is indispensable for contemporary solid-state electronics. The search for thin-film semiconductors that provide simultaneously high carrier mobility and convenient solution-based deposition is also an important research direction, with the resulting expectations of new technologies (such as flexible or wearable computers, large-area high-resolution displays and electronic paper) and lower-cost device fabrication. Here we demonstrate a technique for spin coating ultrathin (approximately 50 A), crystalline and continuous metal chalcogenide films, based on the low-temperature decomposition of highly soluble hydrazinium precursors. We fabricate thin-film field-effect transistors (TFTs) based on semiconducting SnS(2-x)Se(x) films, which exhibit n-type transport, large current densities (>10(5) A cm(-2)) and mobilities greater than 10 cm2 V(-1) s(-1)--an order of magnitude higher than previously reported values for spin-coated semiconductors. The spin-coating technique is expected to be applicable to a range of metal chalcogenides, particularly those based on main group metals, as well as for the fabrication of a variety of thin-film-based devices (for example, solar cells, thermoelectrics and memory devices).