Enabling Fine Sample Rate Settings in DSOs with Time-Interleaved ADCs.

The time-base used by digital storage oscilloscopes allows limited selections of the sample rate, namely constrained to a few integer submultiples of the maximum sample rate. This limitation offers the advantage of simplifying the data transfer from the analog-to-digital converter to the acquisition memory, and of assuring stability performances, expressed in terms of absolute jitter, that are independent of the chosen sample rate. On the counterpart, it prevents an optimal usage of the memory resources of the oscilloscope and compels to post processing operations in several applications. A time-base that allows selecting the sample rate with very fine frequency resolution, in particular as a rational submultiple of the maximum rate, is proposed. The proposal addresses the oscilloscopes with time-interleaved converters, that require a dedicated and multifaceted approach with respect to architectures where a single monolithic converter is in charge of signal digitization. The proposed time-base allows selecting with fine frequency resolution sample rate values up to 200 GHz and beyond, still assuring jitter performances independent of the sample rate selection.

A Night at the OPERA: A Conceptual Framework for an Integrated Distributed Sensor Network-Based System to Figure out Safety Protocols for Animals under Risk of Fire.

Large scale wildfire events that occurred around the world involved a massive loss of animal lives, with a consequent economic impact on agricultural holdings and damages to ecosystems. Preparing animals for a wildfire evacuation requires an extra level of planning, preparedness and coordination, which is missing in the current practice. This paper describes a conceptual framework of an ICT system implemented to support the activities of the Regional Veterinary referral Center for non-epidemic emergencies (CeRVEnE) in the Campania Region for the twofold objectives. On the one hand, it realizes the monitoring of the wooded areas under risk of fire in the so-called "Mount Vesuvius' red zone". On the other hand, it determines the OPtimal Evacuation Route for Animals (OPERA) in case of fire, for each of the reported animal species living in the mentioned red zone. The main innovation of the proposed system lies in its software architecture that aims at integrating a Distributed Sensor Network (DSN), an ad-hoc software to generate timely simulations for fire risk modeling, and a GIS (Geographic Information System) for both the activities of web mapping and OPERA definition. This paper shows some effective preliminary results of the system implementation. The importance of the system mainly lies in its accordance with the so-called "Foresight approach" perspective, that provides models and tools to guarantee the prevention of systematic failure in disaster risk management, and becomes moreover critical in the case of Mount Vesuvius, which hosts a unique combination of both animal and anthropic elements within a delicate natural ecosystem.

Digital Circuit for Seamless Resampling ADC Output Streams.

Fine resolution selection of the sample rate is not available in digital storage oscilloscopes (DSOs), so the user has to rely on offline processing to cope with such need. The paper first discusses digital signal processing based methods that allow changing the sampling rate by means of digital resampling approaches. Then, it proposes a digital circuit that, if included in the acquisition channel of a digital storage oscilloscope, between the internal analog-to-digital converter (ADC) and the acquisition memory, allows the user to select any sampling rate lower than the maximum one with fine resolution. The circuit relies both on the use of a short digital filter with dynamically generated coefficients and on a suitable memory management strategy. The output samples produced by the digital circuit are characterized by a sampling rate that can be incoherent with the clock frequency regulating the memory access. Both a field programmable gate array (FPGA) implementation and an application specific integrated circuit (ASIC) design of the proposed circuit are evaluated.