Variable magnification dual lens electron holography for semiconductor junction profiling and strain mapping.

Dual lens operation for electron holography, which was developed previously (Wang et al., Ultramicroscopy 101 (2004) 63-72; US patent: 7,015,469 B2 (2006)), is re-investigated for bright field (junction profiling) and dark field (strain mapping) electron holography using FEI instrumentation (i.e. F20 and Titan). It is found that dual lens operation provides a wide operational range for electron holography. In addition, the dark field image tilt increases at high objective lens current to include Si <004> diffraction spot. Under the condition of high spatial resolution (1 nm fringe spacing), a large field of view (450 nm), and high fringe contrast (26%) with dual lens operation, a junction map is obtained and strain maps of Si device on <220> and <004> diffraction are acquired. In this paper, a fringe quality number, N', which is number of fringe times fringe contrast, is proposed to estimate the quality of an electron hologram and mathematical reasoning for the N' number is provided.

Off-axis electron holography with a dual-lens imaging system and its usefulness in 2-D potential mapping of semiconductor devices.

A variable magnification electron holography, applicable for two-dimensional (2-D) potential mapping of semiconductor devices, employing a dual-lens imaging system is described. Imaging operation consists of a virtual image formed by the objective lens (OL) and a real image formed in a fixed imaging plane by the objective minilens. Wide variations in field of view (100-900 nm) and fringe spacing (0.7-6 nm) were obtained using a fixed biprism voltage by varying the total magnification of the dual OL system. The dual-lens system allows fringe width and spacing relative to the object to be varied roughly independently from the fringe contrast, resulting in enhanced resolution and sensitivity. The achievable fringe width and spacing cover the targets needed for devices in the semiconductor technology road map from the 350 to 45 nm node. Two-D potential maps for CMOS devices with 220 and 70 nm gate lengths were obtained.