InAs Nanowire Transistors with Multiple, Independent Wrap-Gate Segments.

We report a method for making horizontal wrap-gate nanowire transistors with up to four independently controllable wrap-gated segments. While the step up to two independent wrap-gates requires a major change in fabrication methodology, a key advantage to this new approach, and the horizontal orientation more generally, is that achieving more than two wrap-gate segments then requires no extra fabrication steps. This is in contrast to the vertical orientation, where a significant subset of the fabrication steps needs to be repeated for each additional gate. We show that cross-talk between adjacent wrap-gate segments is negligible despite separations less than 200 nm. We also demonstrate the ability to make multiple wrap-gate transistors on a single nanowire using the exact same process. The excellent scalability potential of horizontal wrap-gate nanowire transistors makes them highly favorable for the development of advanced nanowire devices and possible integration with vertical wrap-gate nanowire transistors in 3D nanowire network architectures.

Fully tunable, non-invasive thermal biasing of gated nanostructures suitable for low-temperature studies.

There is much recent interest in the thermoelectric (TE) characterization of single nanostructures at low temperatures, because such measurements yield information that is complementary to traditional conductance measurements, and because they may lead to novel paradigms for TE energy conversion. However, previously reported techniques for thermal biasing of nanostructures are difficult to use at low temperatures because of unintended global device heating, the lack of ability to continuously tune the thermal bias, or limited compatibility with gating techniques. By placing a heater directly on top of the electrical contact to a single InAs nanowire, we demonstrate fully tunable thermal biases of up to several tens of Kelvin, combined with negligible overall heating of the device, and with full functionality of a back gate, in the temperature range between 4 K and 300 K.

Control and understanding of kink formation in InAs-InP heterostructure nanowires.

Nanowire heterostructures are of special interest for band structure engineering due to an expanded range of defect-free material combinations. However, the higher degree of freedom in nanowire heterostructure growth comes at the expense of challenges related to nanowire-seed particle interactions, such as undesired composition, grading and kink formation. To better understand the mechanisms of kink formation in nanowires, we here present a detailed study of the dependence of heterostructure nanowire morphology on indium pressure, nanowire diameter, and nanowire density. We investigate InAs-InP-InAs heterostructure nanowires grown with chemical beam epitaxy, which is a material system that allows for very abrupt heterointerfaces. Our observations indicate that the critical parameter for kink formation is the availability of indium, and that the resulting morphology is also highly dependent on the length of the InP segment. It is shown that kinking is associated with the formation of an inclined facet at the interface between InP and InAs, which destabilizes the growth and leads to a change in growth direction. By careful tuning of the growth parameters, it is possible to entirely suppress the formation of this inclined facet and thereby kinking at the heterointerface. Our results also indicate the possibility of producing controllably kinked nanowires with a high yield.