3D high resolution imaging for microelectronics: A multi-technique survey on copper pillars.

In microelectronics, recently developed 3D integration offers the possibility to stack the dice or wafers vertically instead of putting their different parts next to one another, in order to save space. As this method becomes of greater interest, the need for 3D imaging techniques becomes higher. We here report a study about different 3D characterization techniques applied to copper pillars, which are used to stack different dice together. Destructive techniques such as FIB/SEM, FIB/FIB, and PFIB/PFIB slice and view protocols have been assessed, as well as non-destructive ones, such as laboratory-based and synchrotron-based computed tomographies. A comparison of those techniques in the specific case of copper pillars is given, taking into account the constraints linked to the microelectronics industry, mainly concerning resolution and sample throughput. Laboratory-based imaging techniques are shown to be relevant in the case of punctual analyses, while synchrotron based tomographies offer highly resolved volumes for larger batches of samples.

Conformal atomic layer deposition of TA-based diffusion barrier film using a novel mono-guanidinate precursor.

In this work, we present elaboration of Ta-based thin films by ALD from a novel tantalum precursor, the eta2-N,N'-isopropylethylguanidinato-tetra-diethylamino tantalum ([eta2-(i)PrNC(NEt2)NEt]Ta(NEt2)4, IEGTDEAT). Ammonia was used as reducing agents. The experimental conditions were optimized by quartz microgravimetry, studying the influence of duration of precursors and purge pulses and the substrate temperature. An optimal deposition temperature of 260 degrees C was showed. Ta-based thin films deposited on planar and patterned substrates showed a perfect conformality and continuity, even at low number of cycles.