4H-SiC MOSFET Threshold Voltage Instability Evaluated via Pulsed High-Temperature Reverse Bias and Negative Gate Bias Stresses.

This paper presents a reliability study of a conventional 650 V SiC planar MOSFET subjected to pulsed HTRB (High-Temperature Reverse Bias) stress and negative HTGB (High-Temperature Gate Bias) stress defined by a TCAD static simulation showing the electric field distribution across the SiC/SiO2 interface. The instability of several electrical parameters was monitored and their drift analyses were investigated. Moreover, the shift of the onset of the Fowler-Nordheim gate injection current under stress conditions provided a reliable method to quantify the trapped charge inside the gate oxide bulk, and it allowed us to determine the real stress conditions. Moreover, it has been demonstrated from the cross-correlation, the TCAD simulation, and the experimental ΔVth and ΔVFN variation that HTGB stress is more severe compared to HTRB. In fact, HTGB showed a 15% variation in both ΔVth and ΔVFN, while HTRB showed only a 4% variation in both ΔVth and ΔVFN. The physical explanation was attributed to the accelerated degradation of the gate insulator in proximity to the source region under HTGB configuration.

Large-Area MoS2 Films Grown on Sapphire and GaN Substrates by Pulsed Laser Deposition.

In this paper, we present the preparation of few-layer MoS2 films on single-crystal sapphire, as well as on heteroepitaxial GaN templates on sapphire substrates, using the pulsed laser deposition (PLD) technique. Detailed structural and chemical characterization of the films were performed using Raman spectroscopy, X-ray photoelectron spectroscopy, X-ray diffraction measurements, and high-resolution transmission electron microscopy. According to X-ray diffraction studies, the films exhibit epitaxial growth, indicating a good in-plane alignment. Furthermore, the films demonstrate uniform thickness on large areas, as confirmed by Raman spectroscopy. The lateral electrical current transport of the MoS2 grown on sapphire was investigated by temperature (T)-dependent sheet resistance and Hall effect measurements, showing a high n-type doping of the semiconducting films (ns from ~1 × 1013 to ~3.4 × 1013 cm-2 from T = 300 K to 500 K), with a donor ionization energy of Ei = 93 ± 8 meV and a mobility decreasing with T. Finally, the vertical current injection across the MoS2/GaN heterojunction was investigated by means of conductive atomic force microscopy, showing the rectifying behavior of the I-V characteristics with a Schottky barrier height of ϕB ≈ 0.36 eV. The obtained results pave the way for the scalable application of PLD-grown MoS2 on GaN in electronics/optoelectronics.

Al2O3 Layers Grown by Atomic Layer Deposition as Gate Insulator in 3C-SiC MOS Devices.

Metal-oxide-semiconductor (MOS) capacitors with Al2O3 as a gate insulator are fabricated on cubic silicon carbide (3C-SiC). Al2O3 is deposited both by thermal and plasma-enhanced Atomic Layer Deposition (ALD) on a thermally grown 5 nm SiO2 interlayer to improve the ALD nucleation and guarantee a better band offset with the SiC. The deposited Al2O3/SiO2 stacks show lower negative shifts of the flat band voltage VFB (in the range of about -3 V) compared with the conventional single SiO2 layer (in the range of -9 V). This lower negative shift is due to the combined effect of the Al2O3 higher permittivity (ε = 8) and to the reduced amount of carbon defects generated during the short thermal oxidation process for the thin SiO2. Moreover, the comparison between thermal and plasma-enhanced ALD suggests that this latter approach produces Al2O3 layers possessing better insulating behavior in terms of distribution of the leakage current breakdown. In fact, despite both possessing a breakdown voltage of 26 V, the T-ALD Al2O3 sample is characterised by a higher current density starting from 15 V. This can be attributable to the slightly inferior quality (in terms of density and defects) of Al2O3 obtained by the thermal approach and, which also explains its non-uniform dC/dV distribution arising by SCM maps.

Nanotechnology for Electronic Materials and Devices.

The historical scaling down of electronics devices is no longer the main goal of the International Roadmap for Devices and Systems [...].

Structural and Insulating Behaviour of High-Permittivity Binary Oxide Thin Films for Silicon Carbide and Gallium Nitride Electronic Devices.

High-κ dielectrics are insulating materials with higher permittivity than silicon dioxide. These materials have already found application in microelectronics, mainly as gate insulators or passivating layers for silicon (Si) technology. However, since the last decade, the post-Si era began with the pervasive introduction of wide band gap (WBG) semiconductors, such as silicon carbide (SiC) and gallium nitride (GaN), which opened new perspectives for high-κ materials in these emerging technologies. In this context, aluminium and hafnium oxides (i.e., Al2O3, HfO2) and some rare earth oxides (e.g., CeO2, Gd2O3, Sc2O3) are promising high-κ binary oxides that can find application as gate dielectric layers in the next generation of high-power and high-frequency transistors based on SiC and GaN. This review paper gives a general overview of high-permittivity binary oxides thin films for post-Si electronic devices. In particular, focus is placed on high-κ binary oxides grown by atomic layer deposition on WBG semiconductors (silicon carbide and gallium nitride), as either amorphous or crystalline films. The impacts of deposition modes and pre- or postdeposition treatments are both discussed. Moreover, the dielectric behaviour of these films is also presented, and some examples of high-κ binary oxides applied to SiC and GaN transistors are reported. The potential advantages and the current limitations of these technologies are highlighted.

Multiscale Investigation of the Structural, Electrical and Photoluminescence Properties of MoS2 Obtained by MoO3 Sulfurization.

In this paper, we report a multiscale investigation of the compositional, morphological, structural, electrical, and optical emission properties of 2H-MoS2 obtained by sulfurization at 800 °C of very thin MoO3 films (with thickness ranging from ~2.8 nm to ~4.2 nm) on a SiO2/Si substrate. XPS analyses confirmed that the sulfurization was very effective in the reduction of the oxide to MoS2, with only a small percentage of residual MoO3 present in the final film. High-resolution TEM/STEM analyses revealed the formation of few (i.e., 2-3 layers) of MoS2 nearly aligned with the SiO2 surface in the case of the thinnest (~2.8 nm) MoO3 film, whereas multilayers of MoS2 partially standing up with respect to the substrate were observed for the ~4.2 nm one. Such different configurations indicate the prevalence of different mechanisms (i.e., vapour-solid surface reaction or S diffusion within the film) as a function of the thickness. The uniform thickness distribution of the few-layer and multilayer MoS2 was confirmed by Raman mapping. Furthermore, the correlative plot of the characteristic A1g-E2g Raman modes revealed a compressive strain (ε ≈ -0.78 ± 0.18%) and the coexistence of n- and p-type doped areas in the few-layer MoS2 on SiO2, where the p-type doping is probably due to the presence of residual MoO3. Nanoscale resolution current mapping by C-AFM showed local inhomogeneities in the conductivity of the few-layer MoS2, which are well correlated to the lateral changes in the strain detected by Raman. Finally, characteristic spectroscopic signatures of the defects/disorder in MoS2 films produced by sulfurization were identified by a comparative analysis of Raman and photoluminescence (PL) spectra with CVD grown MoS2 flakes.

Highly Homogeneous Current Transport in Ultra-Thin Aluminum Nitride (AlN) Epitaxial Films on Gallium Nitride (GaN) Deposited by Plasma Enhanced Atomic Layer Deposition.

This paper reports an investigation of the structural, chemical and electrical properties of ultra-thin (5 nm) aluminum nitride (AlN) films grown by plasma enhanced atomic layer deposition (PE-ALD) on gallium nitride (GaN). A uniform and conformal coverage of the GaN substrate was demonstrated by morphological analyses of as-deposited AlN films. Transmission electron microscopy (TEM) and energy dispersive spectroscopy (EDS) analyses showed a sharp epitaxial interface with GaN for the first AlN atomic layers, while a deviation from the perfect wurtzite stacking and oxygen contamination were detected in the upper part of the film. This epitaxial interface resulted in the formation of a two-dimensional electron gas (2DEG) with a sheet charge density ns ≈ 1.45 × 1012 cm-2, revealed by Hg-probe capacitance-voltage (C-V) analyses. Nanoscale resolution current mapping and current-voltage (I-V) measurements by conductive atomic force microscopy (C-AFM) showed a highly homogeneous current transport through the 5 nm AlN barrier, while a uniform flat-band voltage (VFB ≈ 0.3 V) for the AlN/GaN heterostructure was demonstrated by scanning capacitance microscopy (SCM). Electron transport through the AlN film was shown to follow the Fowler-Nordheim (FN) tunneling mechanism with an average barrier height of <ΦB> = 2.08 eV, in good agreement with the expected AlN/GaN conduction band offset.

Status and Prospects of Cubic Silicon Carbide Power Electronics Device Technology.

Wide bandgap (WBG) semiconductors are becoming more widely accepted for use in power electronics due to their superior electrical energy efficiencies and improved power densities. Although WBG cubic silicon carbide (3C-SiC) displays a modest bandgap compared to its commercial counterparts (4H-silicon carbide and gallium nitride), this material has excellent attributes as the WBG semiconductor of choice for low-resistance, reliable diode and MOS devices. At present the material remains firmly in the research domain due to numerous technological impediments that hamper its widespread adoption. The most obvious obstacle is defect-free 3C-SiC; presently, 3C-SiC bulk and heteroepitaxial (on-silicon) display high defect densities such as stacking faults and antiphase boundaries. Moreover, heteroepitaxy 3C-SiC-on-silicon means low temperature processing budgets are imposed upon the system (max. temperature limited to ~1400 °C) limiting selective doping realisation. This paper will give a brief overview of some of the scientific aspects associated with 3C-SiC processing technology in addition to focussing on the latest state of the art results. A particular focus will be placed upon key process steps such as Schottky and ohmic contacts, ion implantation and MOS processing including reliability. Finally, the paper will discuss some device prototypes (diodes and MOSFET) and draw conclusions around the prospects for 3C-SiC devices based upon the processing technology presented.

Selective Doping in Silicon Carbide Power Devices.

Silicon carbide (SiC) is the most mature wide band-gap semiconductor and is currently employed for the fabrication of high-efficiency power electronic devices, such as diodes and transistors. In this context, selective doping is one of the key processes needed for the fabrication of these devices. This paper concisely reviews the main selective doping techniques for SiC power devices technology. In particular, due to the low diffusivity of the main impurities in SiC, ion implantation is the method of choice to achieve selective doping of the material. Hence, most of this work is dedicated to illustrating the main features of n-type and p-type ion-implantation doping of SiC and discussing the related issues. As an example, one of the main features of implantation doping is the need for post-implantation annealing processes at high temperatures (above 1500 °C) for electrical activation, thus having a notable morphological and structural impact on the material and, hence, on some device parameters. In this respect, some specific examples elucidating the relevant implications on devices' performances are reported in the paper. Finally, a short overview of recently developed non-conventional doping and annealing techniques is also provided, although these techniques are still far from being applied in large-scale devices' manufacturing.

High-Resolution Two-Dimensional Imaging of the 4H-SiC MOSFET Channel by Scanning Capacitance Microscopy.

In this paper, a two-dimensional (2D) planar scanning capacitance microscopy (SCM) method is used to visualize with a high spatial resolution the channel region of large-area 4H-SiC power MOSFETs and estimate the homogeneity of the channel length over the whole device perimeter. The method enabled visualizing the fluctuations of the channel geometry occurring under different processing conditions. Moreover, the impact of the ion implantation parameters on the channel could be elucidated.

An Overview of Normally-Off GaN-Based High Electron Mobility Transistors.

Today, the introduction of wide band gap (WBG) semiconductors in power electronics has become mandatory to improve the energy efficiency of devices and modules and to reduce the overall electric power consumption in the world. Due to its excellent properties, gallium nitride (GaN) and related alloys (e.g., AlxGa1-xN) are promising semiconductors for the next generation of high-power and high-frequency devices. However, there are still several technological concerns hindering the complete exploitation of these materials. As an example, high electron mobility transistors (HEMTs) based on AlGaN/GaN heterostructures are inherently normally-on devices. However, normally-off operation is often desired in many power electronics applications. This review paper will give a brief overview on some scientific and technological aspects related to the current normally-off GaN HEMTs technology. A special focus will be put on the p-GaN gate and on the recessed gate hybrid metal insulator semiconductor high electron mobility transistor (MISHEMT), discussing the role of the metal on the p-GaN gate and of the insulator in the recessed MISHEMT region. Finally, the advantages and disadvantages in the processing and performances of the most common technological solutions for normally-off GaN transistors will be summarized.

Electron trapping at SiO2/4H-SiC interface probed by transient capacitance measurements and atomic resolution chemical analysis.

Studying the electrical and structural properties of the interface of the gate oxide (SiO2) with silicon carbide (4H-SiC) is a fundamental topic, with important implications for understanding and optimising the performances of metal-oxide-semiconductor field effect transistor (MOSFETs). In this paper, near interface oxide traps (NIOTs) in lateral 4H-SiC MOSFETs were investigated combining transient gate capacitance measurements (C-t) and state of the art scanning transmission electron microscopy in electron energy loss spectroscopy (STEM-EELS) with sub-nm resolution. The C-t measurements as a function of temperature indicated that the effective NIOTs discharge time is temperature independent and electrons from NIOTs are emitted toward the semiconductor via-tunnelling. The NIOTs discharge time was modelled also taking into account the interface state density in a tunnelling relaxation model and it allowed us to locate traps within a tunnelling distance of up to 1.3 nm from the SiO2/4H-SiC interface. On the other hand, sub-nm resolution STEM-EELS revealed the presence of a non-abrupt (NA) SiO2/4H-SiC interface. The NA interface shows the re-arrangement of the carbon atoms in a sub-stoichiometric SiO x matrix. A mixed sp2/sp3 carbon hybridization in the NA interface region suggests that the interfacial carbon atoms have lost their tetrahedral SiC coordination.

Conduction Mechanisms at Interface of AlN/SiN Dielectric Stacks with AlGaN/GaN Heterostructures for Normally-off High Electron Mobility Transistors: Correlating Device Behavior with Nanoscale Interfaces Properties.

In this work, the conduction mechanisms at the interface of AlN/SiN dielectric stacks with AlGaN/GaN heterostructures have been studied combining different macroscopic and nanoscale characterizations on bare materials and devices. The AlN/SiN stacks grown on the recessed region of AlGaN/GaN heterostructures have been used as gate dielectric of hybrid metal-insulator-semiconductor high electron mobility transistors (MISHEMTs), showing a normally-off behavior (Vth = +1.2 V), high channel mobility (204 cm2 V-1 s-1), and very good switching behavior (ION/IOFF current ratio of (5-6) × 108 and subthreshold swing of 90 mV/dec). However, the transistors were found to suffer from a positive shift of the threshold voltage during subsequent bias sweeps, which indicates electron trapping in the dielectric stack. To get a complete understanding of the conduction mechanisms and of the charge trapping phenomena in AlN/SiN films, nanoscale current and capacitance measurements by conductive atomic force microscopy (C-AFM) and scanning capacitance microscopy (SCM) have been compared with a macroscopic temperature-dependent characterization of gate current in MIS capacitors. The nanoscale electrical analyses showed the presence of a spatially uniform distribution of electrons trapping states in the insulator and the occurrence of a density of 7 × 108 cm-2 of local and isolated current spots at high bias values. These nanoscale conductive paths can be associated with electrically active defects responsible for the trap-assisted current transport mechanism through the dielectric, observed by the temperature-dependent characterization of the gate current. The results of this study can be relevant for future applications of AlN/SiN bilayers in GaN hybrid MISHEMT technology.

Interface Electrical Properties of Al2O3 Thin Films on Graphene Obtained by Atomic Layer Deposition with an in Situ Seedlike Layer.

High-quality thin insulating films on graphene (Gr) are essential for field-effect transistors (FETs) and other electronics applications of this material. Atomic layer deposition (ALD) is the method of choice to deposit high-κ dielectrics with excellent thickness uniformity and conformal coverage. However, to start the growth on the sp2 Gr surface, a chemical prefunctionalization or the physical deposition of a seed layer are required, which can effect, to some extent, the electrical properties of Gr. In this paper, we report a detailed morphological, structural, and electrical investigation of Al2O3 thin films grown by a two-steps ALD process on a large area Gr membrane residing on an Al2O3-Si substrate. This process consists of the H2O-activated deposition of a Al2O3 seed layer a few nanometers in thickness, performed in situ at 100 °C, followed by ALD thermal growth of Al2O3 at 250 °C. The optimization of the low-temperature seed layer allowed us to obtain a uniform, conformal, and pinhole-free Al2O3 film on Gr by the second ALD step. Nanoscale-resolution mapping of the current through the dielectric by conductive atomic force microscopy (CAFM) demonstrated an excellent laterally uniformity of the film. Raman spectroscopy measurements indicated that the ALD process does not introduce defects in Gr, whereas it produces a partial compensation of Gr unintentional p-type doping, as confirmed by the increase of Gr sheet resistance (from ∼300 Ω/sq in pristine Gr to ∼1100 Ω/sq after Al2O3 deposition). Analysis of the transfer characteristics of Gr field-effect transistors (GFETs) allowed us to evaluate the relative dielectric permittivity (ε = 7.45) and the breakdown electric field (EBD = 7.4 MV/cm) of the Al2O3 film as well as the transconductance and the holes field-effect mobility (∼1200 cm2 V-1 s-1). A special focus has been given to the electrical characterization of the Al2O3-Gr interface by the analysis of high frequency capacitance-voltage measurements, which allowed us to elucidate the charge trapping and detrapping phenomena due to near-interface and interface oxide traps.

Nanoscale probing of the lateral homogeneity of donors concentration in nitridated SiO2/4H-SiC interfaces.

In this paper, nanoscale resolution scanning capacitance microscopy (SCM) and local capacitance-voltage measurements were used to probe the interfacial donor concentration in SiO2/4H-SiC systems annealed in N2O. Such nitrogen-based annealings are commonly employed to passivate SiO2/SiC interface traps, and result both in the incorporation of N-related donors in SiC and in the increase of the mobility in the inversion layer in 4H-SiC MOS-devices. From our SCM measurements, a spatially inhomogeneous donor distribution was observed in the SiO2/4H-SiC system subjected to N2O annealing. Hence, the effect of a phosphorus implantation before the oxide deposition and N2O annealing was also evaluated. In this case, besides an increased average donor concentration, an improvement of the lateral homogeneity of the active doping was also detected. The possible implications of such a pre-implantation doping of the near-interface region on 4H-SiC MOS-devices are discussed.

Nanoscale electrical and structural modification induced by rapid thermal oxidation of AlGaN/GaN heterostructures.

In this paper, the structural and electrical modifications induced, in the nanoscale, by a rapid thermal oxidation process on AlGaN/GaN heterostructures, are investigated. A local rapid oxidation (900 ° C in O2, 10 min) localized under the anode region of an AlGaN/GaN diode enabled a reduction of the leakage current with respect to a standard Schottky contact. The insulating properties of the near-surface oxidized layer were probed by a nanoscale electrical characterization using scanning probe microscopy techniques. The structural characterization indicated the formation of a thin uniform oxide layer on the surface, with preferential oxidation paths along V-shaped defects penetrating through the AlGaN/GaN interface. The oxidation process resulted in an expansion of the lattice parameters due to the incorporation of oxygen atoms, accompanied by an increase of the crystal mosaicity. As a consequence, a decrease of the sheet carrier density of the two-dimensional electron gas and a positive shift of the threshold voltage are observed. The results provide useful insights for a possible future integration of rapid oxidation processes during GaN device fabrication.

Micro- and nanoscale electrical characterization of large-area graphene transferred to functional substrates.

Chemical vapour deposition (CVD) on catalytic metals is one of main approaches for high-quality graphene growth over large areas. However, a subsequent transfer step to an insulating substrate is required in order to use the graphene for electronic applications. This step can severely affect both the structural integrity and the electronic properties of the graphene membrane. In this paper, we investigated the morphological and electrical properties of CVD graphene transferred onto SiO2 and on a polymeric substrate (poly(ethylene-2,6-naphthalene dicarboxylate), briefly PEN), suitable for microelectronics and flexible electronics applications, respectively. The electrical properties (sheet resistance, mobility, carrier density) of the transferred graphene as well as the specific contact resistance of metal contacts onto graphene were investigated by using properly designed test patterns. While a sheet resistance R sh ≈ 1.7 kΩ/sq and a specific contact resistance ρc ≈ 15 kΩ·µm have been measured for graphene transferred onto SiO2, about 2.3× higher R sh and about 8× higher ρc values were obtained for graphene on PEN. High-resolution current mapping by torsion resonant conductive atomic force microscopy (TRCAFM) provided an insight into the nanoscale mechanisms responsible for the very high ρc in the case of graphene on PEN, showing a ca. 10× smaller "effective" area for current injection than in the case of graphene on SiO2.

A look underneath the SiO2/4H-SiC interface after N2O thermal treatments.

The electrical compensation effect of the nitrogen incorporation at the SiO2/4H-SiC (p-type) interface after thermal treatments in ambient N2O is investigated employing both scanning spreading resistance microscopy (SSRM) and scanning capacitance microscopy (SCM). SSRM measurements on p-type 4H-SiC areas selectively exposed to N2O at 1150 °C showed an increased resistance compared to the unexposed ones; this indicates the incorporation of electrically active nitrogen-related donors, which compensate the p-type doping in the SiC surface region. Cross-sectional SCM measurements on SiO2/4H-SiC metal/oxide/semiconductor (MOS) devices highlighted different active carrier concentration profiles in the first 10 nm underneath the insulator-substrate interface depending on the SiO2/4H-SiC roughness. The electrically active incorporated nitrogen produces both a compensation of the acceptors in the substrate and a reduction of the interface state density (D it). This result can be correlated with the 4H-SiC surface configuration. In particular, lower D it values were obtained for a SiO2/SiC interface on faceted SiC than on planar SiC. These effects were explained in terms of the different surface configuration in faceted SiC that enables the simultaneous exposition at the interface of atomic planes with different orientations.

Nanoscale characterization of electrical transport at metal/3C-SiC interfaces.

In this work, the transport properties of metal/3C-SiC interfaces were monitored employing a nanoscale characterization approach in combination with conventional electrical measurements. In particular, using conductive atomic force microscopy allowed demonstrating that the stacking fault is the most pervasive, electrically active extended defect at 3C-SiC(111) surfaces, and it can be electrically passivated by an ultraviolet irradiation treatment. For the Au/3C-SiC Schottky interface, a contact area dependence of the Schottky barrier height (ΦB) was found even after this passivation, indicating that there are still some electrically active defects at the interface. Improved electrical properties were observed in the case of the Pt/3C-SiC system. In this case, annealing at 500°C resulted in a reduction of the leakage current and an increase of the Schottky barrier height (from 0.77 to 1.12 eV). A structural analysis of the reaction zone carried out by transmission electron microscopy [TEM] and X-ray diffraction showed that the improved electrical properties can be attributed to a consumption of the surface layer of SiC due to silicide (Pt2Si) formation. The degradation of Schottky characteristics at higher temperatures (up to 900°C) could be ascribed to the out-diffusion and aggregation of carbon into clusters, observed by TEM analysis.

Scanning Probe Microscopy on heterogeneous CaCu3Ti4O12 thin films.

The conductive atomic force microscopy provided a local characterization of the dielectric heterogeneities in CaCu3Ti4O12 (CCTO) thin films deposited by MOCVD on IrO2 bottom electrode. In particular, both techniques have been employed to clarify the role of the inter- and sub-granular features in terms of conductive and insulating regions. The microstructure and the dielectric properties of CCTO thin films have been studied and the evidence of internal barriers in CCTO thin films has been provided. The role of internal barriers and the possible explanation for the extrinsic origin of the giant dielectric response in CCTO has been evaluated.