All van der Waals Semiconducting PtSe2 Field Effect Transistors with Low Contact Resistance Graphite Electrodes.

Contact resistance is a multifaceted challenge faced by the 2D materials community. Large Schottky barrier heights and gap-state pinning are active obstacles that require an integrated approach to achieve the development of high-performance electronic devices based on 2D materials. In this work, we present semiconducting PtSe2 field effect transistors with all-van-der-Waals electrode and dielectric interfaces. We use graphite contacts, which enable high ION/IOFF ratios up to 109 with currents above 100 µA µm-1 and mobilities of 50 cm2 V-1 s-1 at room temperature and over 400 cm2 V-1 s-1 at 10 K. The devices exhibit high stability with a maximum hysteresis width below 36 mV nm-1. The contact resistance at the graphite-PtSe2 interface is found to be below 700 Ω µm. Our results present PtSe2 as a promising candidate for the realization of high-performance 2D circuits built solely with 2D materials.

High-κ Wide-Gap Layered Dielectric for Two-Dimensional van der Waals Heterostructures.

van der Waals heterostructures of two-dimensional materials have unveiled frontiers in condensed matter physics, unlocking unexplored possibilities in electronic and photonic device applications. However, the investigation of wide-gap, high-κ layered dielectrics for devices based on van der Waals structures has been relatively limited. In this work, we demonstrate an easily reproducible synthesis method for the rare-earth oxyhalide LaOBr, and we exfoliate it as a 2D layered material with a measured static dielectric constant of 9 and a wide bandgap of 5.3 eV. Furthermore, our research demonstrates that LaOBr can be used as a high-κ dielectric in van der Waals field-effect transistors with high performance and low interface defect concentrations. Additionally, it proves to be an attractive choice for electrical gating in excitonic devices based on 2D materials. Our work demonstrates the versatile realization and functionality of 2D systems with wide-gap and high-κ van der Waals dielectric environments.

Over- and Undercoordinated Atoms as a Source of Electron and Hole Traps in Amorphous Silicon Nitride (a-Si3N4).

Silicon nitride films are widely used as the charge storage layer of charge trap flash (CTF) devices due to their high charge trap densities. The nature of the charge trapping sites in these materials responsible for the memory effect in CTF devices is still unclear. Most prominently, the Si dangling bond or K-center has been identified as an amphoteric trap center. Nevertheless, experiments have shown that these dangling bonds only make up a small portion of the total density of electrical active defects, motivating the search for other charge trapping sites. Here, we use a machine-learned force field to create model structures of amorphous Si3N4 by simulating a melt-and-quench procedure with a molecular dynamics algorithm. Subsequently, we employ density functional theory in conjunction with a hybrid functional to investigate the structural properties and electronic states of our model structures. We show that electrons and holes can localize near over- and under-coordinated atoms, thereby introducing defect states in the band gap after structural relaxation. We analyze these trapping sites within a nonradiative multi-phonon model by calculating relaxation energies and thermodynamic charge transition levels. The resulting defect parameters are used to model the potential energy curves of the defect systems in different charge states and to extract the classical energy barrier for charge transfer. The high energy barriers for charge emission compared to the vanishing barriers for charge capture at the defect sites show that intrinsic electron traps can contribute to the memory effect in charge trap flash devices.

Observation of Rich Defect Dynamics in Monolayer MoS2.

Defects play a pivotal role in limiting the performance and reliability of nanoscale devices. Field-effect transistors (FETs) based on atomically thin two-dimensional (2D) semiconductors such as monolayer MoS2 are no exception. Probing defect dynamics in 2D FETs is therefore of significant interest. Here, we present a comprehensive insight into various defect dynamics observed in monolayer MoS2 FETs at varying gate biases and temperatures. The measured source-to-drain currents exhibit random telegraph signals (RTS) owing to the transfer of charges between the semiconducting channel and individual defects. Based on the modeled temperature and gate bias dependence, oxygen vacancies or aluminum interstitials are probable defect candidates. Several types of RTSs are observed including anomalous RTS and giant RTS indicating local current crowding effects and rich defect dynamics in monolayer MoS2 FETs. This study explores defect dynamics in large area-grown monolayer MoS2 with ALD-grown Al2O3 as the gate dielectric.

DELMEP: a deep learning algorithm for automated annotation of motor evoked potential latencies.

The analysis of motor evoked potentials (MEPs) generated by transcranial magnetic stimulation (TMS) is crucial in research and clinical medical practice. MEPs are characterized by their latency and the treatment of a single patient may require the characterization of thousands of MEPs. Given the difficulty of developing reliable and accurate algorithms, currently the assessment of MEPs is performed with visual inspection and manual annotation by a medical expert; making it a time-consuming, inaccurate, and error-prone process. In this study, we developed DELMEP, a deep learning-based algorithm to automate the estimation of MEP latency. Our algorithm resulted in a mean absolute error of about 0.5 ms and an accuracy that was practically independent of the MEP amplitude. The low computational cost of the DELMEP algorithm allows employing it in on-the-fly characterization of MEPs for brain-state-dependent and closed-loop brain stimulation protocols. Moreover, its learning ability makes it a particularly promising option for artificial-intelligence-based personalized clinical applications.

Machine learning interatomic potential for silicon-nitride (Si3N4) by active learning.

Silicon nitride (Si3N4) is an extensively used material in the automotive, aerospace, and semiconductor industries. However, its widespread use is in contrast to the scarce availability of reliable interatomic potentials that can be employed to study various aspects of this material on an atomistic scale, particularly its amorphous phase. In this work, we developed a machine learning interatomic potential, using an efficient active learning technique, combined with the Gaussian approximation potential (GAP) method. Our strategy is based on using an inexpensive empirical potential to generate an initial dataset of atomic configurations, for which energies and forces were recalculated with density functional theory (DFT); thereafter, a GAP was trained on these data and an iterative re-training algorithm was used to improve it by learning on-the-fly. When compared to DFT, our potential yielded a mean absolute error of 8 meV/atom in energy calculations for a variety of liquid and amorphous structures and a speed-up of molecular dynamics simulations by 3-4 orders of magnitude, while achieving a first-rate agreement with experimental results. Our potential is publicly available in an open-access repository.

Hybrid 2D-CMOS microchips for memristive applications.

Exploiting the excellent electronic properties of two-dimensional (2D) materials to fabricate advanced electronic circuits is a major goal for the semiconductor industry1,2. However, most studies in this field have been limited to the fabrication and characterization of isolated large (more than 1 µm2) devices on unfunctional SiO2-Si substrates. Some studies have integrated monolayer graphene on silicon microchips as a large-area (more than 500 µm2) interconnection3 and as a channel of large transistors (roughly 16.5 µm2) (refs. 4,5), but in all cases the integration density was low, no computation was demonstrated and manipulating monolayer 2D materials was challenging because native pinholes and cracks during transfer increase variability and reduce yield. Here, we present the fabrication of high-integration-density 2D-CMOS hybrid microchips for memristive applications-CMOS stands for complementary metal-oxide-semiconductor. We transfer a sheet of multilayer hexagonal boron nitride onto the back-end-of-line interconnections of silicon microchips containing CMOS transistors of the 180 nm node, and finalize the circuits by patterning the top electrodes and interconnections. The CMOS transistors provide outstanding control over the currents across the hexagonal boron nitride memristors, which allows us to achieve endurances of roughly 5 million cycles in memristors as small as 0.053 µm2. We demonstrate in-memory computation by constructing logic gates, and measure spike-timing dependent plasticity signals that are suitable for the implementation of spiking neural networks. The high performance and the relatively-high technology readiness level achieved represent a notable advance towards the integration of 2D materials in microelectronic products and memristive applications.

Challenges for Nanoscale CMOS Logic Based on Two-Dimensional Materials.

For ultra-scaled technology nodes at channel lengths below 12 nm, two-dimensional (2D) materials are a potential replacement for silicon since even atomically thin 2D semiconductors can maintain sizable mobilities and provide enhanced gate control in a stacked channel nanosheet transistor geometry. While theoretical projections and available experimental prototypes indicate great potential for 2D field effect transistors (FETs), several major challenges must be solved to realize CMOS logic circuits based on 2D materials at the wafer scale. This review discusses the most critical issues and benchmarks against the targets outlined for the 0.7 nm node in the International Roadmap for Devices and Systems scheduled for 2034. These issues are grouped into four areas; device scaling, the formation of low-resistive contacts to 2D semiconductors, gate stack design, and wafer-scale process integration. Here, we summarize recent developments in these areas and identify the most important future research questions which will have to be solved to allow for industrial adaptation of the 2D technology.

Epitaxial Growth of Crystalline CaF2 on Silicene.

Silicene is one of the most promising two-dimensional (2D) materials for the realization of next-generation electronic devices, owing to its high carrier mobility and band gap tunability. To fully control its electronic properties, an external electric field needs to be applied perpendicularly to the 2D lattice, thus requiring the deposition of an insulating layer that directly interfaces silicene, without perturbing its bidimensional nature. A promising material candidate is CaF2, which is known to form a quasi van der Waals interface with 2D materials as well as to maintain its insulating properties even at ultrathin scales. Here we investigate the epitaxial growth of thin CaF2 layers on different silicene phases by means of molecular beam epitaxy. Through electron diffraction images, we clearly show that CaF2 can be grown epitaxially on silicene even at low temperatures, with its domains fully aligned to the lattice of the underlying 2D structure. Moreover, in situ X-ray photoelectron spectroscopy data evidence that, upon CaF2 deposition, no changes in the chemical state of the silicon atoms can be detected, proving that no Si-Ca or Si-F bonds are formed. This clearly shows that the 2D layer is pristinely preserved underneath the insulating layer. Polarized Raman experiments show that silicene undergoes a structural change upon interaction with CaF2; however, it retains its two-dimensional character without transitioning to a sp3-hybridized silicon. For the first time, we have shown that CaF2 and silicene can be successfully interfaced, paving the way for the integration of silicon-based 2D materials in functional devices.

Improving stability in two-dimensional transistors with amorphous gate oxides by Fermi-level tuning.

Electronic devices based on two-dimensional semiconductors suffer from limited electrical stability because charge carriers originating from the semiconductors interact with defects in the surrounding insulators. In field-effect transistors, the resulting trapped charges can lead to large hysteresis and device drifts, particularly when common amorphous gate oxides (such as silicon or hafnium dioxide) are used, hindering stable circuit operation. Here, we show that device stability in graphene-based field-effect transistors with amorphous gate oxides can be improved by Fermi-level tuning. We deliberately tune the Fermi level of the channel to maximize the energy distance between the charge carriers in the channel and the defect bands in the amorphous aluminium gate oxide. Charge trapping is highly sensitive to the energetic alignment of the Fermi level of the channel with the defect band in the insulator, and thus, our approach minimizes the amount of electrically active border traps without the need to reduce the total number of traps in the insulator.

Special Issue on Miniaturized Transistors, Volume II.

Due to the great success of the initial Special Issue on Miniaturized Transistors [...].

Perspective of 2D Integrated Electronic Circuits: Scientific Pipe Dream or Disruptive Technology?

Within the last decade, considerable efforts have been devoted to fabricating transistors utilizing 2D semiconductors. Also, small circuits consisting of a few transistors have been demonstrated, including inverters, ring oscillators, and static random access memory cells. However, for industrial applications, both time-zero and time-dependent variability in the performance of the transistors appear critical. While time-zero variability is primarily related to immature processing, time-dependent drifts are dominated by charge trapping at defects located at the channel/insulator interface and in the insulator itself, which can substantially degrade the stability of circuits. At the current state of the art, 2D transistors typically exhibit a few orders of magnitude higher trap densities than silicon devices, which considerably increases their time-dependent variability, resulting in stability and yield issues. Here, the stability of currently available 2D electronics is carefully evaluated using circuit simulations to determine the impact of transistor-related issues on the overall circuit performance. The results suggest that while the performance parameters of transistors based on certain material combinations are already getting close to being competitive with Si technologies, a reduction in variability and defect densities is required. Overall, the criteria for parameter variability serve as guidance for evaluating the future development of 2D technologies.

Insulators for 2D nanoelectronics: the gap to bridge.

Nanoelectronic devices based on 2D materials are far from delivering their full theoretical performance potential due to the lack of scalable insulators. Amorphous oxides that work well in silicon technology have ill-defined interfaces with 2D materials and numerous defects, while 2D hexagonal boron nitride does not meet required dielectric specifications. The list of suitable alternative insulators is currently very limited. Thus, a radically different mindset with respect to suitable insulators for 2D technologies may be required. We review possible solution scenarios like the creation of clean interfaces, production of native oxides from 2D semiconductors and more intensive studies on crystalline insulators.

Dielectric Properties of Ultrathin CaF2 Ionic Crystals.

Mechanically exfoliated 2D hexagonal boron nitride (h-BN) is currently the preferred dielectric material to interact with graphene and 2D transition metal dichalcogenides in nanoelectronic devices, as they form a clean van der Waals interface. However, h-BN has a low dielectric constant (≈3.9), which in ultrascaled devices results in high leakage current and premature dielectric breakdown. Furthermore, the synthesis of h-BN using scalable methods, such as chemical vapor deposition, requires very high temperatures (>900 °C) , and the resulting h-BN stacks contain abundant few-atoms-wide amorphous regions that decrease its homogeneity and dielectric strength. Here it is shown that ultrathin calcium fluoride (CaF2 ) ionic crystals could be an excellent solution to mitigate these problems. By applying >3000 ramped voltage stresses and several current maps at different locations of the samples via conductive atomic force microscopy, it is statistically demonstrated that ultrathin CaF2 shows much better dielectric performance (i.e., homogeneity, leakage current, and dielectric strength) than SiO2 , TiO2 , and h-BN. The main reason behind this behavior is that the cubic crystalline structure of CaF2 is continuous and free of defects over large regions, which prevents the formation of electrically weak spots.

Semi-Automated Extraction of the Distribution of Single Defects for nMOS Transistors.

Miniaturization of metal-oxide-semiconductor field effect transistors (MOSFETs) is typically beneficial for their operating characteristics, such as switching speed and power consumption, but at the same time miniaturization also leads to increased variability among nominally identical devices. Adverse effects due to oxide traps in particular become a serious issue for device performance and reliability. While the average number of defects per device is lower for scaled devices, the impact of the oxide defects is significantly more pronounced than in large area transistors. This combination enables the investigation of charge transitions of single defects. In this study, we perform random telegraph noise (RTN) measurements on about 300 devices to statistically characterize oxide defects in a Si/SiO 2 technology. To extract the noise parameters from the measurements, we make use of the Canny edge detector. From the data, we obtain distributions of the step heights of defects, i.e., their impact on the threshold voltage of the devices. Detailed measurements of a subset of the defects further allow us to extract their vertical position in the oxide and their trap level using both analytical estimations and full numerical simulations. Contrary to published literature data, we observe a bimodal distribution of step heights, while the extracted distribution of trap levels agrees well with recent studies.

Editorial for the Special Issue on Miniaturized Transistors.

Complementary Metal Oxide Semiconductor (CMOS) devices and fabrication techniques have enabled tremendous technological advancements in a short period of time [...].

Characterization of Single Defects in Ultrascaled MoS2 Field-Effect Transistors.

MoS2 has received a lot of attention lately as a semiconducting channel material for electronic devices, in part due to its large band gap as compared to that of other 2D materials. Yet, the performance and reliability of these devices are still severely limited by defects which act as traps for charge carriers, causing severely reduced mobilities, hysteresis, and long-term drift. Despite their importance, these defects are only poorly understood. One fundamental problem in defect characterization is that due to the large defect concentration only the average response to bias changes can be measured. On the basis of such averaged data, a detailed analysis of their properties and identification of particular defect types are difficult. To overcome this limitation, we here characterize single defects on MoS2 devices by performing measurements on ultrascaled transistors (∼65 × 50 nm) which contain only a few defects. These single defects are characterized electrically at varying gate biases and temperatures. The measured currents contain random telegraph noise, which is due to the transfer of charge between the channel of the transistors and individual defects, visible only due to the large impact of a single elementary charge on the local electrostatics in these small devices. Using hidden Markov models for statistical analysis, we extract the charge capture and emission times of a number of defects. By comparing the bias-dependence of the measured capture and emission times to the prediction of theoretical models, we provide simple rules to distinguish oxide traps from adsorbates on these back-gated devices. In addition, we give simple expressions to estimate the vertical and energetic positions of the defects. Using the methods presented in this work, it is possible to locate the sources of performance and reliability limitations in 2D devices and to probe defect distributions in oxide materials with 2D channel materials.

Long-Term Stability and Reliability of Black Phosphorus Field-Effect Transistors.

Black phosphorus has been recently suggested as a very promising material for use in 2D field-effect transistors. However, due to its poor stability under ambient conditions, this material has not yet received as much attention as for instance MoS2. We show that the recently demonstrated Al2O3 encapsulation leads to highly stable devices. In particular, we report our long-term study on highly stable black phosphorus field-effect transistors, which show stable device characteristics for at least eight months. This high stability allows us to perform a detailed analysis of their reliability with respect to hysteresis as well as the arguably most important reliability issue in silicon technologies, the bias-temperature instability. We find that the hysteresis in these transistors depends strongly on the sweep rate and temperature. Moreover, the hysteresis dynamics in our devices are reproducible over a long time, which underlines their high reliability. Also, by using detailed physical models for oxide traps developed for Si technologies, we are able to capture the channel electrostatics of the black phosphorus FETs and determine the position of the defect energy band. Finally, we demonstrate that both hysteresis and bias-temperature instabilities are due to thermally activated charge trapping/detrapping by oxide traps and can be reduced if the device is covered by Teflon-AF.

Role of hydrogen in volatile behaviour of defects in SiO2-based electronic devices.

Charge capture and emission by point defects in gate oxides of metal-oxide-semiconductor field-effect transistors (MOSFETs) strongly affect reliability and performance of electronic devices. Recent advances in experimental techniques used for probing defect properties have led to new insights into their characteristics. In particular, these experimental data show a repeated dis- and reappearance (the so-called volatility) of the defect-related signals. We use multiscale modelling to explain the charge capture and emission as well as defect volatility in amorphous SiO2 gate dielectrics. We first briefly discuss the recent experimental results and use a multiphonon charge capture model to describe the charge-trapping behaviour of defects in silicon-based MOSFETs. We then link this model to ab initio calculations that investigate the three most promising defect candidates. Statistical distributions of defect characteristics obtained from ab initio calculations in amorphous SiO2 are compared with the experimentally measured statistical properties of charge traps. This allows us to suggest an atomistic mechanism to explain the experimentally observed volatile behaviour of defects. We conclude that the hydroxyl-E' centre is a promising candidate to explain all the observed features, including defect volatility.