Design and measurements of low power multichannel chip for recording and stimulation of neural activity.

A 64-channel Neuro-Stimulation-Recording chip named NRS64 for neural activity measurements has been designed and tested. The NRS64 occupies 5×5 mm² of silicon area and consumes only 25 µW/channel. A low cut-off frequency can be tuned in the 60 mHz-100 Hz range while a high cut-off frequency can be set to 4.7 kHz or 12 kHz. A voltage gain can be set to 139 V/V or 1100 V/V. A measured input referenced noise is 3.7 µV rms in 100 Hz-12 kHz band and 7.6 µV rms in 3 Hz-12 kHz band. A digital correction is used in each channel to tune the low cut-off frequency and offset voltage. Each channel is equipped additionally with a stimulation circuit with an artifact cancellation circuit. The stimulation circuit can be set with 8-bit resolution in six different ranges from 500 nA-512 µA range.

Design and measurements of 64-channel ASIC for neural signal recording.

This paper presents the design and measurements of a low noise multi-channel front-end electronics for recording extra-cellular neuronal signals using microelectrode arrays. The integrated circuit contains 64 readout channels and was fabricated in CMOS 0.18 microm technology. A single readout channel is built of an AC coupling circuit at the input, a low noise preamplifier, a band-pass filter and a second amplifier. In order to reduce the number of output lines, the 64 analog signals from readout channels are multiplexed to a single output by an analog multiplexer. The chip is optimized for low noise and matching performance with the possibility of cut-off frequencies tuning. The low cut-off frequency can be tuned in the 1 Hz-60 Hz range and the high cut-off frequency can be tuned in the 3.5 kHz-15 kHz range. For the nominal gain setting at 44 dB and power dissipation per single channel of 220 microW the equivalent input noise is in the range from 6 microV-11 microV rms depending on the band-pass filter settings. The chip has good uniformity concerning the spread of its electrical parameters from channel to channel. The spread of gain calculated as standard deviation to mean value is about 4.4% and the spread of the low cut-off frequency is on the same level. The chip occupies 5x2.3 mm(2) of silicon area.

Contrast cancellation technique applied to digital x-ray imaging using silicon strip detectors.

Dual-energy mammographic imaging experimental tests have been performed using a compact dichromatic imaging system based on a conventional x-ray tube, a mosaic crystal, and a 384-strip silicon detector equipped with full-custom electronics with single photon counting capability. For simulating mammal tissue, a three-component phantom, made of Plexiglass, polyethylene, and water, has been used. Images have been collected with three different pairs of x-ray energies: 16-32 keV, 18-36 keV, and 20-40 keV. A Monte Carlo simulation of the experiment has also been carried out using the MCNP-4C transport code. The Alvarez-Macovski algorithm has been applied both to experimental and simulated data to remove the contrast between two of the phantom materials so as to enhance the visibility of the third one.

A low noise multichannel integrated circuit for recording neuronal signals using microelectrode arrays.

This paper reports on the development of a fully integrated 32-channel integrated circuit (IC) for recording neuronal signals in neurophysiological experiments using microelectrode arrays. The IC consists of 32 channels of low-noise preamplifiers and bandpass filters, and an output analog multiplexer. The continuous-time RC active filters have a typical passband of 20-2000 Hz; the low and the high cut-off frequencies can be separately controlled by external reference currents. This chip provides a satisfactory signal-to-noise ratio for neuronal signals with amplitudes greater than 50 microV. For the nominal passband setting, an equivalent input noise of 3 microV rms has been achieved. A single channel occupies 0.35 mm(2) of silicon area and dissipates 1.7 mW of power. The chip was fabricated in a 0.7 microm CMOS process.