New improved fractional order differentiator models based on optimized digital differentiators.

Different evolutionary algorithms (EAs), namely, particle swarm optimization (PSO), genetic algorithm (GA), and PSO-GA hybrid optimization, have been used to optimize digital differential operators so that these can be better fitted to exemplify their new improved fractional order differentiator counterparts. First, the paper aims to provide efficient 2nd and 3rd order operators in connection with process of minimization of error fitness function by registering mean, median, and standard deviation values in different random iterations to ascertain the best results among them, using all the abovementioned EAs. Later, these optimized operators are discretized for half differentiator models for utilizing their restored qualities inhibited from their optimization. Simulation results present the comparisons of the proposed half differentiators with the existing and amongst different models based on 2nd and 3rd order optimized operators. Proposed half differentiators have been observed to approximate the ideal half differentiator and also outperform the existing ones reasonably well in complete range of Nyquist frequency.

A modified implementation of tristate inverter based static master-slave flip-flop with improved power-delay-area product.

The paper introduces novel architectures for implementation of fully static master-slave flip-flops for low power, high performance, and high density. Based on the proposed structure, traditional C(2)MOS latch (tristate inverter/clocked inverter) based flip-flop is implemented with fewer transistors. The modified C(2)MOS based flip-flop designs mC(2)MOSff1 and mC(2)MOSff2 are realized using only sixteen transistors each while the number of clocked transistors is also reduced in case of mC(2)MOSff1. Postlayout simulations indicate that mC(2)MOSff1 flip-flop shows 12.4% improvement in PDAP (power-delay-area product) when compared with transmission gate flip-flop (TGFF) at 16X capacitive load which is considered to be the best design alternative among the conventional master-slave flip-flops. To validate the correct behaviour of the proposed design, an eight bit asynchronous counter is designed to layout level. LVS and parasitic extraction were carried out on Calibre, whereas layouts were implemented using IC station (Mentor Graphics). HSPICE simulations were used to characterize the transient response of the flip-flop designs in a 180 nm/1.8 V CMOS technology. Simulations were also performed at 130 nm, 90 nm, and 65 nm to reveal the scalability of both the designs at modern process nodes.

Small polaron hopping conduction mechanism in Fe doped LaMnO3.

The structural and electrical transport properties of LaMn(1-x)Fe(x)O(3) (0.1 ≤ x ≤ 0.6) bulk samples have been investigated. The powder x-ray diffraction patterns at room temperature show that all samples are formed in single phase. The temperature dependent resistivity data have been fitted with the Mott's variable-range hopping (VRH) model for an entire studied range of the temperature (77-300 K) to calculate the hopping distance (R(h)) and the density of states at Fermi level (N(E(F))). It is found that all parameters vary systematically with the increase in Fe concentration. Moreover, the resistivity data were also fitted in the small polaron hopping (SPH) model. The non-adiabatic SPH conduction mechanism is followed by all samples. This type conduction mechanism is far accompanied by subtle electronically induced structural changes involving in Fe-O-Fe and Fe-O-Mn bond angles and bond lengths. Thus we suggest that the transport properties can be explained according to the additional localization of charge carriers induced by Fe doping.