Integrated optical deserialiser time sampling based SiGe photoreceiver.

A novel photoreceiver architecture enabling parallel processing in the electronic domain of a high-speed optical signal is demonstrated. This allows the electronics to operate at significantly lower frequency than the optical signal and hence reduce power consumption and the impact of parasitics. The photoreceiver performs optical time sampling with four integrated SiGe photodetectors connected in series by waveguide delay lines. Four variations of the optical time sampling receiver are designed and demonstrated which differ by the data rate (10 Gb/s and 20 Gb/s) and silicon delay waveguide loss (2.5 dB/cm and 0.2 dB/cm). The bit error rate performance of the photodetectors in the receiver was measured individually and reached a performance below 1 × 10⁻¹° at an input optical power between 4.8 and 6.3 dBm through an off-chip 50 Ω load at the output. After O/E conversion, the electrical signal (one segment of 2¹5 - 1 PRBS data) from each of the photodetector is processed without errors at a quarter of the bit rate, leading to an overall more power efficient receiver front-end.

Simultaneous high-capacity optical and microwave data transmission over metal waveguides.

The implementation of power efficient and high throughput chip-to-chip interconnects is necessary to keep pace with the bandwidth demands in high-performance computing platforms. In recent years, considerable effort has been made to optimize inter-chip communications using traditional copper waveguides. Also, optical links are extensively investigated as an alternative technology for fast and efficient data routing. For the first time, we experimentally demonstrate simultaneous microwave and optical high-speed data transmission over metallic waveguides embedded in polymer. The demonstration is significant as it merges two layers of communications onto the same structure towards increased aggregated bandwidth, and energy-efficient data movement.

A 16 GHz silicon-based monolithic balanced photodetector with on-chip capacitors for 25 Gbaud front-end receivers.

In this paper, a Germanium-on-Silicon balanced photodetector (BPD) with integrated biasing capacitors is demonstrated for highly compact monolithic 100 Gb/s coherent receivers or 25 Gbaud front-end receivers for differential or quadrature phase shift keying. The balanced photodetector has a bandwidth of approximately 16.2 GHz at a reverse bias of -4.5 V. The balanced photodetector exhibits a common mode rejection ratio (CMRR) of 30 dB. For balanced detection of return-to-zero (RZ) differential phase shift keying (DPSK) signal, the photodetector has a sensitivity of -6.95 dBm at the BER of 10(-12). For non-return-to-zero (NRZ) on off keying (OOK) signal, the measured BER is 1.0 × 10(-12) for a received power of -1.65 dBm at 25 Gb/s and 9.9 × 10(-5) for -0.34 dBm at 30 Gb/s. The total footprint area of the monolithic front-end receiver is less than 1 mm(2). The BPD is packaged onto a ceramic substrate with two DC and one RF connectors exhibits a bandwidth of 15.9 GHz.