Outwitting the series resistance in scanning spreading resistance microscopy.

The performance of nanoelectronics devices critically depends on the distribution of active dopants inside these structures. For this reason, dopant profiling has been defined as one of the major metrology challenges by the international technology roadmap of semiconductors. Scanning spreading resistance microscopy (SSRM) has evolved as one of the most viable approaches over the last decade due to its excellent spatial resolution, sensitivity and quantification accuracy. However, in case of advanced device architectures like fins and nanowires a proper measurement of the spreading resistance is often hampered by the increasing impact of parasitic series resistances (e.g. bulk series resistance) arising from the confined nature of the aforementioned structures. In order to overcome this limitation we report in this paper the development and implementation of a novel SSRM mode (fast Fourier transform-SSRM: FFT-SSRM) which essentially decouples the spreading resistance from parasitic series resistance components. We show that this can be achieved by a force modulation (leading to a modulated spreading resistance signal) in combination with a lock-in deconvolution concept. In this paper we first introduce the principle of operation of the technique. We discuss in detail the underlying physical mechanisms as well as the technical implementation on a state-of-the-art atomic force microscope (AFM). We demonstrate the performance of FFT-SSRM and its ability to remove substantial series resistance components in practice. Eventually, the possibility of decoupling the spreading resistance from the intrinsic probe resistance will be demonstrated and discussed.

Carbon nanotube growth for through silicon via application.

Through silicon via (TSV) technology is key for next generation three-dimensional integrated circuits, and carbon nanotubes (CNT) provide a promising alternative to metal for filling the TSV. Three catalyst preparation methods for achieving CNT growth from the bottom of the TSV are investigated. Compared with sputtering and evaporation, catalyst deposition using dip-coating in a FeCl2 solution is found to be a more efficient method for realizing a bottom-up filling of the TSV (aspect ratio 5 or 10) with CNT. The CNT bundles grown in 5 min exceed the 50 µm length of the TSV and are multi-wall CNT with three to eight walls. The CNT bundles inside the TSV were electrically characterized by creating a direct contact using a four-point nanoprober setup. A low resistance of the CNT bundle of 69.7 Ω (297 Ω) was measured when the CNT bundle was contacted midway along (over the full length of) the 25 µm deep TSV. The electrical characterization in combination with the good filling of the TSV demonstrates the potential use of CNT in fully integrated TSV applications.

Quantitative three-dimensional carrier mapping in nanowire-based transistors using scanning spreading resistance microscopy.

The performance of nanoelectronic devices critically depends on the distribution of charge carriers inside such structures. High-vacuum scanning spreading resistance microscopy (HV-SSRM) has established as the method of choice for quantitative 2D-carrier mapping in nanoscale devices during the last decade. However, due to the 3D-nature of these nanoscale device architectures, dopant incorporation and dopant diffusion mechanisms can vary for any of the three dimensions, depending on the particular processes used. Therefore, mapping of carriers in three dimensions with high spatial resolution is inevitable to study and understand the distribution of active dopants in confined 3D-volumes and ultimately to support the process development of next generation devices. In this work, we present for the first time an approach to extend the capabilities of SSRM from an inherent 2D-carrier profiling technique towards a quantitative 3D-characterization technique based on the example of a nanowire (NW)-based heterojunction (SiGe-Si) tunneling transistor. In order to implement a 3D-methodology with a 2D-imaging technique, we acquired 2D-carrier concentration maps on successive cross-section planes through the device of interest. This was facilitated by arranging several devices in a staggered array, allowing to produce a series of cross-sections with incremental offset by a single cleave. A dedicated interpolation algorithm especially suited for structures with rotational symmetry like NWs was developed in order to reconstruct a 3D-carrier distribution map. The validity of the method was assessed by proving the absence of variations in carrier distribution in the third dimension, as expected for NWs etched into a blanket stack.

Electrical tomography using atomic force microscopy and its application towards carbon nanotube-based interconnects.

The fabrication and integration of low-resistance carbon nanotubes (CNTs) for interconnects in future integrated circuits requires characterization techniques providing structural and electrical information at the nanometer scale. In this paper we present a slice-and-view approach based on electrical atomic force microscopy. Material removal achieved by successive scanning using doped ultra-sharp full-diamond probes, manufactured in-house, enables us to acquire two-dimensional (2D) resistance maps originating from different depths (equivalently different CNT lengths) on CNT-based interconnects. Stacking and interpolating these 2D resistance maps results in a three-dimensional (3D) representation (tomogram). This allows insight from a structural (e.g. size, density, distribution, straightness) and electrical point of view simultaneously. By extracting the resistance evolution over the length of an individual CNT we derive quantitative information about the resistivity and the contact resistance between the CNT and bottom electrode.

Observation of diameter dependent carrier distribution in nanowire-based transistors.

The successful implementation of nanowire (NW) based field-effect transistors (FET) critically depends on quantitative information about the carrier distribution inside such devices. Therefore, we have developed a method based on high-vacuum scanning spreading resistance microscopy (HV-SSRM) which allows two-dimensional (2D) quantitative carrier profiling of fully integrated silicon NW-based tunnel-FETs (TFETs) with 2 nm spatial resolution. The key elements of our characterization procedure are optimized NW cleaving and polishing steps, the use of in-house fabricated ultra-sharp diamond tips, measurements in high vacuum and a dedicated quantification procedure accounting for the Schottky-like tip-sample contact affected by surface states. In the case of the implanted TFET source regions we find a strong NW diameter dependence of conformality, junction abruptness and gate overlap, quantitatively in agreement with process simulations. In contrast, the arsenic doped drain regions reveal an unexpected NW diameter dependent dopant deactivation. The observed lower drain doping for smaller diameters is reflected in the device characteristics by lower TFET off-currents, as measured experimentally and confirmed by device simulations.

Optimization of multi-walled carbon nanotube-metal contacts by electrical stressing.

We present experimental data on the contact resistances of three different metal probes, tungsten, palladium and indium, with chemical vapour deposited (CVD) multi-wall carbon nanotubes (MWCNTs). We demonstrate that there is an irreversible modification of the contacts following electrical stressing whereby the circuit resistance converges towards its optimal value prior to current-induced tube failure. Once the probe-MWCNT contact is broken, subsequent recontact experiments reveal that the circuit resistance returns to its initial high level, demonstrating that the modification occurs at the probe contact location and not elsewhere in the circuit. Contact studies with the different metals reveal that Pd metal provides the lowest resistance contact to the MWCNT in our sample.