A Real-Time Vital-Sign Monitoring in the Physical Domain on a Mixed-Signal Reconfigurable Platform.

This work presents a mixed-signal physical-compu-tation-electronics for monitoring three vital signs; namely heart rate, blood pressure, and blood oxygen saturation; from electrocardiography, arterial blood pressure, and photoplethysmography signals in real-time. The computational circuits are implemented on a reconfigurable and programmable signal-processing platform, namely field-programmable analog array (FPAA). The design leverages the core enabling technology of FPAA, namely floating-gate CMOS devices, and an on-chip low-power microcontroller to achieve energy-efficiency while not compromising accuracy. The custom physical-computation-electronics operating in CMOS subthreshold region, performs low-level (i.e., physiologically-relevant feature extraction) and high-level (i.e., detecting arrhythmia) signal processing in an energy-efficient manner. The on-chip microcontroller is used (1) in the programming mode for controlling the charge storage at the analog-memory elements to introduce patient-dependency into the system and (2) in the run mode to quantify the vital signs. The system has been validated against digital computation results from MATLAB using datasets collected from three healthy subjects and datasets from the MIT/BIH open source database. Based on all recordings in the MIT/BIH database, ECG R-peak detection sensitivity is 94.2%. The processor detects arrhythmia in three MIT/BIH recordings with an average sensitivity of 96.2%. The cardiac processor achieves an average percentage mean error bounded by 3.75%, 6.27%, and 7.3% for R-R duration, systolic blood pressure, and oxygen saturation level calculations; respectively. The power consumption of the ECG, blood-pressure and photo-plethysmography processing circuitry are 126 nW, 251 nW and 1.44 µW respectively in a 350 nm process. Overall, the cardiac processor consumes 1.82 µW.

Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain.

Neuromorphic engineering (NE) encompasses a diverse range of approaches to information processing that are inspired by neurobiological systems, and this feature distinguishes neuromorphic systems from conventional computing systems. The brain has evolved over billions of years to solve difficult engineering problems by using efficient, parallel, low-power computation. The goal of NE is to design systems capable of brain-like computation. Numerous large-scale neuromorphic projects have emerged recently. This interdisciplinary field was listed among the top 10 technology breakthroughs of 2014 by the MIT Technology Review and among the top 10 emerging technologies of 2015 by the World Economic Forum. NE has two-way goals: one, a scientific goal to understand the computational properties of biological neural systems by using models implemented in integrated circuits (ICs); second, an engineering goal to exploit the known properties of biological systems to design and implement efficient devices for engineering applications. Building hardware neural emulators can be extremely useful for simulating large-scale neural models to explain how intelligent behavior arises in the brain. The principal advantages of neuromorphic emulators are that they are highly energy efficient, parallel and distributed, and require a small silicon area. Thus, compared to conventional CPUs, these neuromorphic emulators are beneficial in many engineering applications such as for the porting of deep learning algorithms for various recognitions tasks. In this review article, we describe some of the most significant neuromorphic spiking emulators, compare the different architectures and approaches used by them, illustrate their advantages and drawbacks, and highlight the capabilities that each can deliver to neural modelers. This article focuses on the discussion of large-scale emulators and is a continuation of a previous review of various neural and synapse circuits (Indiveri et al., 2011). We also explore applications where these emulators have been used and discuss some of their promising future applications.

Long-Term Results of Acetabular Reconstruction Using Ganz Acetabular Rings.

BACKGROUND: Our study examines the long-term results of acetabular reconstruction using the Ganz acetabular reinforcement ring (GRR) in total hip arthroplasty. METHODS: Between 1998 and 2001, 135 hips (119 revision and 16 primary arthroplasties) were consecutively implanted with a GRR at our hospital. The average age was 65 years (range, 26-90). Clinical and radiographic evaluations were carried out. Long-term survivorship was estimated using a competing risks analysis, and multivariate survivorship using Cox regression model was used to identify risk factors for implant failure. RESULTS: At a mean follow-up of 16 years (range, 15-18), 3 patients were lost to follow-up and 19 had implant failure: 4 aseptic loosenings without re-revision, 4 septic, and 11 aseptic re-revisions. Survival was estimated at 86% after 16 years (95% confidence interval [CI], 78.5%-90.9%) using radiographic loosening or revision for any reason as the end point. Using aseptic loosening as the end point, the survival was estimated at 91.2% after 16 years (95% CI, 84.5%-95.0%). Multivariate analysis revealed that age at surgery was a significant risk factor for failure of the GRR. With acetabular revision or loosening as the end point, patients ≤60 years had 71.6% (95% CI, 53%-82.8%) and older patients had 92.2% (95% CI, 84%-96.2%) probability of implant survival after a mean 16-year follow-up. The median Harris Hip Scores and Western Ontario and McMaster Universities Osteoarthritis Index scores were 77 and 64.5, respectively, and mean Numerical Pain Rating Scale score was 1.6 at final follow-up. CONCLUSION: Our long-term study showed acceptable survival and functional results using the GRR in older patients, while young patients had less favorable survival.

Hodgkin-Huxley Neuron and FPAA Dynamics.

We present the experimental silicon results on the dynamics of a Hodgkin-Huxley neuron implemented on a reconfigurable platform. The circuit has been inspired by the similarity between biology and silicon, by modeling ion channels and their time constants. Another significant motivation behind this paper is to make the system available to circuit designers as well as users in the neuroscience community. The open-source tool infrastructure and a remote system ease the accessibility of our system to a number of users. We demonstrate the reproducibility of the results by replicating the dynamics across different boards along with responses from different inputs and with different parameters. The reconfigurability enables one to make use of a single primary design to obtain a variety of results. The measurements are taken from the system compiled on a field programmable analog array fabricated on a 350-nm process.

Corrigendum: Large-Scale Neuromorphic Spiking Array Processors: A Quest to Mimic the Brain.

[This corrects the article DOI: 10.3389/fnins.2018.00891.].

Reconfigurable analog classifier for knee-joint rehabilitation.

We present a System-On-Chip Field Programmable Analog Array (FPAA) for analyzing and processing the signals off an accelerometer for a wearable joint health assessment device. FPAAs have been shown to compute with an efficiency of 1000 times, as well as area efficiencies of 100 times, more than digital solutions. This work presents a low power signal processing system which allows us to extract features from the output of the accelerometer. These features are used by the classifier, implemented using a vector matrix multiplication and a two output 1-winner-take-all, to detect flexion and extension cycles in the subject. The compiled design consumes 0.636 µW of power for the front end analog signal processing chain where as the single layer classifier uses 13 µW of power. Thus the system is highly suitable for wearable applications where power consumption is a major concern. The current FPAA is fabricated in a 0.35 µm CMOS process and is operated at a power supply of 2.5 volts. The Gm-C filters and other circuits are operated in the subthreshold regime of the transistor to obtain the highest transconductance to current ratio offered by the process.

Optimal sparse approximation with integrate and fire neurons.

Sparse approximation is a hypothesized coding strategy where a population of sensory neurons (e.g. V1) encodes a stimulus using as few active neurons as possible. We present the Spiking LCA (locally competitive algorithm), a rate encoded Spiking Neural Network (SNN) of integrate and fire neurons that calculate sparse approximations. The Spiking LCA is designed to be equivalent to the nonspiking LCA, an analog dynamical system that converges on a ℓ(1)-norm sparse approximations exponentially. We show that the firing rate of the Spiking LCA converges on the same solution as the analog LCA, with an error inversely proportional to the sampling time. We simulate in NEURON a network of 128 neuron pairs that encode 8 × 8 pixel image patches, demonstrating that the network converges to nearly optimal encodings within 20 ms of biological time. We also show that when using more biophysically realistic parameters in the neurons, the gain function encourages additional ℓ(0)-norm sparsity in the encoding, relative both to ideal neurons and digital solvers.

Compiling probabilistic, bio-inspired circuits on a field programmable analog array.

A FIELD PROGRAMMABLE ANALOG ARRAY (FPAA) IS PRESENTED AS AN ENERGY AND COMPUTATIONAL EFFICIENCY ENGINE: a mixed mode processor for which functions can be compiled at significantly less energy costs using probabilistic computing circuits. More specifically, it will be shown that the core computation of any dynamical system can be computed on the FPAA at significantly less energy per operation than a digital implementation. A stochastic system that is dynamically controllable via voltage controlled amplifier and comparator thresholds is implemented, which computes Bernoulli random variables. From Bernoulli variables it is shown exponentially distributed random variables, and random variables of an arbitrary distribution can be computed. The Gillespie algorithm is simulated to show the utility of this system by calculating the trajectory of a biological system computed stochastically with this probabilistic hardware where over a 127X performance improvement over current software approaches is shown. The relevance of this approach is extended to any dynamical system. The initial circuits and ideas for this work were generated at the 2008 Telluride Neuromorphic Workshop.

Capacitive micromachined ultrasonic transducer arrays as tunable acoustic metamaterials.

Capacitive Micromachined Ultrasonic Transducers (CMUTs) operating in immersion support dispersive evanescent waves due to the subwavelength periodic structure of electrostatically actuated membranes in the array. Evanescent wave characteristics also depend on the membrane resonance which is modified by the externally applied bias voltage, offering a mechanism to tune the CMUT array as an acoustic metamaterial. The dispersion and tunability characteristics are examined using a computationally efficient, mutual radiation impedance based approach to model a finite-size array and realistic parameters of variation. The simulations are verified, and tunability is demonstrated by experiments on a linear CMUT array operating in 2-12 MHz range.

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-µm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-µm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 µm and 251 µm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

Neuron array with plastic synapses and programmable dendrites.

We describe a novel neuromorphic chip architecture that models neurons for efficient computation. Traditional architectures of neuron array chips consist of large scale systems that are interfaced with AER for implementing intra- or inter-chip connectivity. We present a chip that uses AER for inter-chip communication but uses fast, reconfigurable FPGA-style routing with local memory for intra-chip connectivity. We model neurons with biologically realistic channel models, synapses and dendrites. This chip is suitable for small-scale network simulations and can also be used for sequence detection, utilizing directional selectivity properties of dendrites, ultimately for use in word recognition.

Finding a roadmap to achieve large neuromorphic hardware systems.

Neuromorphic systems are gaining increasing importance in an era where CMOS digital computing techniques are reaching physical limits. These silicon systems mimic extremely energy efficient neural computing structures, potentially both for solving engineering applications as well as understanding neural computation. Toward this end, the authors provide a glimpse at what the technology evolution roadmap looks like for these systems so that Neuromorphic engineers may gain the same benefit of anticipation and foresight that IC designers gained from Moore's law many years ago. Scaling of energy efficiency, performance, and size will be discussed as well as how the implementation and application space of Neuromorphic systems are expected to evolve over time.