RESUMO
An estimated 70% of the electricity in the United States currently passes through power conversion electronics, and this percentage is projected to increase eventually to up to 100%. At a global scale, wide adoption of highly efficient power electronics technologies is thus anticipated to have a major impact on worldwide energy consumption. As described in this perspective, for power conversion, outstanding thermal management for semiconductor devices is one key to unlocking this potentially massive energy savings. Integrated microscale cooling has been positively identified for such thermal management of future high-heat-flux, i.e., 1 kW/cm2, wide-bandgap (WBG) semiconductor devices. In this work, we connect this advanced cooling approach to the energy impact of using WBG devices and further present a techno-economic analysis to clarify the projected status of performance, manufacturing approaches, fabrication costs, and remaining barriers to the adoption of such cooling technology.
RESUMO
This letter solves a major hurdle that mars photolithography-based fabrication of micro-mesoscale structures in silicon. Conventional photolithography is usually performed on smooth, flat wafer surfaces to lay a 2D design and subsequently etch it to create single-level features. It is, however, unable to process non-flat surfaces or already etched wafers and create more than one level in the structure. In this study, we have described a novel cleanroom-based process flow that allows for easy creation of such multi-level, hierarchical 3D structures in a substrate. This is achieved by introducing an ultra-thin sacrificial silicon dioxide hardmask layer on the substrate which is first 3D patterned via multiple rounds of lithography. This 3D pattern is then scaled vertically by a factor of 200-300 and transferred to the substrate underneath via a single shot deep etching step. The proposed method is also easily characterizable-using features of different topographies and dimensions, the etch rates and selectivities were quantified; this characterization information was later used while fabricating specific target structures. Furthermore, this study comprehensively compares the novel pattern transfer technique to already existing methods of creating multi-level structures, like grayscale lithography and chip stacking. The proposed process was found to be cheaper, faster, and easier to standardize compared to other methods-this made the overall process more reliable and repeatable. We hope it will encourage more research into hybrid structures that hold the key to dramatic performance improvements in several micro-mesoscale devices.
