Modern microprocessor built from complementary carbon nanotube transistors.

Electronics is approaching a major paradigm shift because silicon transistor scaling no longer yields historical energy-efficiency benefits, spurring research towards beyond-silicon nanotechnologies. In particular, carbon nanotube field-effect transistor (CNFET)-based digital circuits promise substantial energy-efficiency benefits, but the inability to perfectly control intrinsic nanoscale defects and variability in carbon nanotubes has precluded the realization of very-large-scale integrated systems. Here we overcome these challenges to demonstrate a beyond-silicon microprocessor built entirely from CNFETs. This 16-bit microprocessor is based on the RISC-V instruction set, runs standard 32-bit instructions on 16-bit data and addresses, comprises more than 14,000 complementary metal-oxide-semiconductor CNFETs and is designed and fabricated using industry-standard design flows and processes. We propose a manufacturing methodology for carbon nanotubes, a set of combined processing and design techniques for overcoming nanoscale imperfections at macroscopic scales across full wafer substrates. This work experimentally validates a promising path towards practical beyond-silicon electronic systems.

Low-Temperature Side Contact to Carbon Nanotube Transistors: Resistance Distributions Down to 10 nm Contact Length.

Carbon nanotube field-effect transistors (CNFETs) promise to improve the energy efficiency, speed, and transistor density of very large scale integration circuits owing to the intrinsic thin channel body and excellent charge transport properties of carbon nanotubes. Low-temperature fabrication (e.g., <400 °C) is a key enabler for the monolithic three-dimensional (3D) integration of CNFET digital logic into a device technology platform that overcomes memory bandwidth bottlenecks for data-abundant applications such as big-data analytics and machine learning. However, high contact resistance for short CNFET contacts has been a major roadblock to establishing CNFETs as a viable technology because the contact resistance, in series with the channel resistance, reduces the on-state current of CNFETs. Additionally, the variation in contact resistance remains unstudied for short contacts and will further degrade the energy efficiency and speed of CNFET circuits. In this work, we investigate by experiments the contact resistance and statistical variation of room-temperature fabricated CNFET contacts down to 10 nm contact lengths. These CNFET contacts are ∼15 nm shorter than the state-of-the-art Si CMOS "7 nm node" contact length, allowing for multiple generations of future scaling of the transistor-contacted gate pitch. For the 10 nm contacts, we report contact resistance values down to 6.5 kΩ per source/drain contact for a single carbon nanotube (CNT) with a median contact resistance of 18.2 kΩ. The 10 nm contacts reduce the CNFET current by as little as 13% at VDS = 0.7 V compared with the best reported 200 nm contacts to date, corroborated by results in this work. Our analysis of RC from 232 single-CNT CNFETs between the long-contact (e.g., 200 nm) and short-contact (e.g., 10 nm) regimes quantifies the resistance variation and projects the impact on CNFET current variability versus the number of CNT in the transistor. The resistance distribution reveals contact-length-dependent RC variations become significant below 20 nm contact length. However, a larger source of CNFET resistance variation is apparent at all contact lengths used in this work. To further investigate the origins of this contact-length-independent resistance variation, we analyze the variation of RC in arrays of identical CNFETs along a single CNT of constant diameter and observe the random occurrence of high  RC, even on correlated CNFETs.

Tunable n-Type Doping of Carbon Nanotubes through Engineered Atomic Layer Deposition HfOX Films.

Although digital systems fabricated from carbon-nanotube-based field-effect transistors (CNFETs) promise significant energy efficiency benefits, realizing these benefits requires a complementary CNFET technology, i.e., CNFET CMOS, comprising both PMOS and NMOS CNFETs. Furthermore, this CNFET CMOS process must be robust ( e.g., air-stable), tunable ( e.g., ability to control CNFET threshold voltages), and silicon CMOS compatible (to integrate within existing manufacturing facilities and process flows). Despite many efforts, such a silicon CMOS compatible CNT doping strategy for forming NMOS CNFETs does not exist. Techniques today are either not air-stable (using reactive low work function metals), not solid-state or silicon CMOS compatible (employing soluble molecular dopants in ionic solutions), or have not demonstrated precise control over the amount of doping (for setting threshold voltage,  VT). Here, we demonstrate an electrostatic doping technique that meets all of these requirements. The key to our technique is leveraging atomic layer deposition (ALD) to encapsulate CNTs with nonstoichiometric oxides. We show that ALD allows for precise control of oxide stoichiometry, which translates to direct control of the amount of CNT doping. We experimentally demonstrate the ability to modulate the strength of the p-type conduction branch by >2500× (measured as the change in current at fixed bias), realize NMOS CNFETs with n-type conduction ∼500× stronger than p-type conduction (also measured by the relative current at fixed biases), and tune VT over a ∼1.5 V range. Moreover, our technique is compatible with other doping schemes; as an illustration, we combine electrostatic doping and low work function contact engineering to achieve CNFET CMOS with symmetric NMOS and PMOS ( i.e., CNFET ON-current for NMOS and PMOS is within 6% of each other). Thus, this work realizes a solid-state, air-table, very large scale integration and silicon CMOS compatible doping strategy, enabling integration of CNFET CMOS within standard fabrication processes today.

Three-dimensional integration of nanotechnologies for computing and data storage on a single chip.

The computing demands of future data-intensive applications will greatly exceed the capabilities of current electronics, and are unlikely to be met by isolated improvements in transistors, data storage technologies or integrated circuit architectures alone. Instead, transformative nanosystems, which use new nanotechnologies to simultaneously realize improved devices and new integrated circuit architectures, are required. Here we present a prototype of such a transformative nanosystem. It consists of more than one million resistive random-access memory cells and more than two million carbon-nanotube field-effect transistors-promising new nanotechnologies for use in energy-efficient digital logic circuits and for dense data storage-fabricated on vertically stacked layers in a single chip. Unlike conventional integrated circuit architectures, the layered fabrication realizes a three-dimensional integrated circuit architecture with fine-grained and dense vertical connectivity between layers of computing, data storage, and input and output (in this instance, sensing). As a result, our nanosystem can capture massive amounts of data every second, store it directly on-chip, perform in situ processing of the captured data, and produce 'highly processed' information. As a working prototype, our nanosystem senses and classifies ambient gases. Furthermore, because the layers are fabricated on top of silicon logic circuitry, our nanosystem is compatible with existing infrastructure for silicon-based technologies. Such complex nano-electronic systems will be essential for future high-performance and highly energy-efficient electronic systems.

Hysteresis-Free Carbon Nanotube Field-Effect Transistors.

While carbon nanotube (CNT) field-effect transistors (CNFETs) promise high-performance and energy-efficient digital systems, large hysteresis degrades these potential CNFET benefits. As hysteresis is caused by traps surrounding the CNTs, previous works have shown that clean interfaces that are free of traps are important to minimize hysteresis. Our previous findings on the sources and physics of hysteresis in CNFETs enabled us to understand the influence of gate dielectric scaling on hysteresis. To begin with, we validate through simulations how scaling the gate dielectric thickness results in greater-than-expected benefits in reducing hysteresis. Leveraging this insight, we experimentally demonstrate reducing hysteresis to <0.5% of the gate-source voltage sweep range using a very large-scale integration compatible and solid-state technology, simply by fabricating CNFETs with a thin effective oxide thickness of 1.6 nm. However, even with negligible hysteresis, large subthreshold swing is still observed in the CNFETs with multiple CNTs per transistor. We show that the cause of large subthreshold swing is due to threshold voltage variation between individual CNTs. We also show that the source of this threshold voltage variation is not explained solely by variations in CNT diameters (as is often ascribed). Rather, other factors unrelated to the CNTs themselves (i.e., process variations, random fixed charges at interfaces) are a significant factor in CNT threshold voltage variations and thus need to be further improved.

Hysteresis in Carbon Nanotube Transistors: Measurement and Analysis of Trap Density, Energy Level, and Spatial Distribution.

We present a measurement technique, which we call the Pulsed Time-Domain Measurement, for characterizing hysteresis in carbon nanotube field-effect transistors, and demonstrate its applicability for a broad range of 1D and 2D nanomaterials beyond carbon nanotubes. The Pulsed Time-Domain Measurement enables the quantification (density, energy level, and spatial distribution) of charged traps responsible for hysteresis. A physics-based model of the charge trapping process for a carbon nanotube field-effect transistor is presented and experimentally validated using the Pulsed Time-Domain Measurement. Leveraging this model, we discover a source of traps (surface traps) unique to devices with low-dimensional channels such as carbon nanotubes and nanowires (beyond interface traps which exist in today's silicon field-effect transistors). The different charge trapping mechanisms for interface traps and surface traps are studied based on their temperature dependencies. Through these advances, we are able to quantify the interface trap density for carbon nanotube field-effect transistors (∼3 × 10(13) cm(-2) eV(-1) near midgap), and compare this against a range of previously studied dielectric/semiconductor interfaces.

Carbon nanotube computer.

The miniaturization of electronic devices has been the principal driving force behind the semiconductor industry, and has brought about major improvements in computational power and energy efficiency. Although advances with silicon-based electronics continue to be made, alternative technologies are being explored. Digital circuits based on transistors fabricated from carbon nanotubes (CNTs) have the potential to outperform silicon by improving the energy-delay product, a metric of energy efficiency, by more than an order of magnitude. Hence, CNTs are an exciting complement to existing semiconductor technologies. Owing to substantial fundamental imperfections inherent in CNTs, however, only very basic circuit blocks have been demonstrated. Here we show how these imperfections can be overcome, and demonstrate the first computer built entirely using CNT-based transistors. The CNT computer runs an operating system that is capable of multitasking: as a demonstration, we perform counting and integer-sorting simultaneously. In addition, we implement 20 different instructions from the commercial MIPS instruction set to demonstrate the generality of our CNT computer. This experimental demonstration is the most complex carbon-based electronic system yet realized. It is a considerable advance because CNTs are prominent among a variety of emerging technologies that are being considered for the next generation of highly energy-efficient electronic systems.