A Novel Deep-Trench Super-Junction SiC MOSFET with Improved Specific On-Resistance.

In this paper, a novel 4H-SiC deep-trench super-junction MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor) with a split-gate is proposed and theoretically verified by Sentaurus TCAD simulations. A deep trench filled with P-poly-Si combined with the P-SiC region leads to a charge balance effect. Instead of a full-SiC P region in conventional super-junction MOSFET, this new structure reduces the P region in a super-junction MOSFET, thus helping to lower the specific on-resistance. As a result, the figure of merit (FoM, BV2/Ron,sp) of the proposed new structure is 642% and 39.65% higher than the C-MOS and the SJ-MOS, respectively.

A Novel Asymmetric Trench SiC Metal-Oxide-Semiconductor Field-Effect Transistor with a Poly-Si/SiC Heterojunction Diode for Optimizing Reverse Conduction Performance.

In this paper, a novel asymmetric trench SiC MOSFET with a Poly-Si/SiC heterojunction diode (HJD-ATMOS) is designed to improve its reverse conduction characteristics and switching performance. This structure features an integrated heterojunction diode, which improves body diode characteristics without affecting device static characteristics. The heterojunction diode acts as a freewheeling diode during reverse conduction, reducing the cut-in voltage (Vcut-in) to a lower level than conventional asymmetric trench SiC MOSFET (C-ATMOS), while maintaining a similar breakdown voltage. Meanwhile, the split gate structure reduces gate-to-drain charge (Qgd). Through TCAD simulation, the HJD-ATMOS decreases Vcut-in by 53.04% compared to the C-ATMOS. Both Qgd and switching loss are reduced, with a decrease of 31.91% in Qgd and 40.29% in switching loss.

The Influence of Special Environments on SiC MOSFETs.

In this work, the influences of special environments (hydrogen gas and high temperature, high humidity environments) on the performance of three types of SiC MOSFETs are investigated. The results reveal several noteworthy observations. Firstly, after 500 h in a hydrogen gas environment, all the SiC MOSFETs exhibited a negative drift in threshold voltage, accompanied by an increase in maximum transconductance and drain current (@ VGS/VDS = 13 V/3 V). This phenomenon can be attributed to that the hydrogen atoms can increase the positive fixed charges in the oxide and increase the electron mobility in the channel. In addition, high temperature did not intensify the impact of hydrogen on the devices and electron mobility. Instead, prolonged exposure to high temperatures may induce stress on the SiO2/SiC interface, leading to a decrease in electron mobility, subsequently reducing the transconductance and drain current (@ VGS/VDS = 13 V/3 V). The high temperature, high humidity environment can cause a certain negative drift in the devices' threshold voltage. With the increasing duration of the experiment, the maximum transconductance and drain current (@ VGS/VDS = 18V (20 V)/3 V) gradually decreased. This may be because the presence of moisture can lead to corrosion of the devices' metal contacts and interconnects, which can increase the devices' resistance and lead to a decrease in the devices' maximum transconductance and drain current.

A SiC Planar MOSFET with an Embedded MOS-Channel Diode to Improve Reverse Conduction and Switching.

A novel split-gate SiC MOSFET with an embedded MOS-channel diode for enhanced third-quadrant and switching performances is proposed and studied using TCAD simulations in this paper. During the freewheeling period, the MOS-channel diode with a low potential barrier constrains the reverse current flow through it. Therefore, the suggested device not only has a low diode cut-in voltage but also entirely suppresses the intrinsic body diode, which will cause bipolar deterioration. In order to clarify the barrier-lowering effect of the MOS-channel diode, an analytical model is proposed. The calibrated simulation results demonstrate that the diode cut-in voltage of the proposed device is decreased from the conventional voltage of 2.7 V to 1.2 V. In addition, due to the split-gate structure, the gate-to-drain charge (QGD) of the proposed device is 20 nC/cm2, and the reverse-transfer capacitance (CGD) is 14 pF/cm2, which are lower than the QGD of 230 nC/cm2 and the CGD of 105 pF/cm2 for the conventional one. Therefore, a better high-frequency figure-of-merit and lower switching loss are obtained.

Simulation Studies on Single-Event Effects and the Mechanisms of SiC VDMOS from a Structural Perspective.

The single-event effect reliability issue is one of the most critical concerns in the context of space applications for SiC VDMOS. In this paper, the SEE characteristics and mechanisms of the proposed deep trench gate superjunction (DTSJ), conventional trench gate superjunction (CTSJ), conventional trench gate (CT), and conventional planar gate (CT) SiC VDMOS are comprehensively analyzed and simulated. Extensive simulations demonstrate the maximum SET current peaks of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS, which are 188 mA, 218 mA, 242 mA, and 255 mA, with a bias voltage VDS of 300 V and LET = 120 MeV·cm2/mg, respectively. The total charges of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS collected at the drain are 320 pC, 1100 pC, 885 pC, and 567 pC, respectively. A definition and calculation of the charge enhancement factor (CEF) are proposed. The CEF values of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS are 43, 160, 117, and 55, respectively. Compared with CTSJ-, CT-, and CP SiC VDMOS, the total charge and CEF of the DTSJ SiC VDMOS are reduced by 70.9%, 62.4%, 43.6% and 73.1%, 63.2%, and 21.8%, respectively. The maximum SET lattice temperature of the DTSJ SiC VDMOS is less than 2823 K under the wide operating conditions of a drain bias voltage VDS ranging from 100 V to 1100 V and a LET value ranging from 1 MeV·cm2/mg to 120 MeV·cm2/mg, while the maximum SET lattice temperatures of the other three SiC VDMOS significantly exceed 3100 K. The SEGR LET thresholds of DTSJ-, CTSJ-, CT-, and CP SiC VDMOS are approximately 100 MeV·cm2/mg, 15 MeV·cm2/mg, 15 MeV·cm2/mg, and 60 MeV·cm2/mg, respectively, while the value of VDS = 1100 V.

Analysis and Hardening of SEGR in Trench VDMOS with Termination Structure.

Single-event gate-rupture (SEGR) in the trench vertical double-diffused power MOSFET (VDMOS) occurs at a critical bias voltage during heavy-ion experiments. Fault analysis demonstrates that the hot spot is located at the termination of the VDMOS, and the gate oxide in the termination region has been damaged. The SEGR-hardened termination with multiple implantation regions is proposed and simulated using the Sentaurus TCAD. The multiple implantation regions are introduced, leading to an increase in the distance between the gate oxide and the hole accumulation region, as well as a decrease in the resistivity of the hole conductive path. This approach is effective in reducing the electric field of the gate oxide to below the calculated critical field, and results in a lower electric field than the conventional termination.

Effect of Electro-Thermo-Mechanical Coupling Stress on Top-Cooled E-Mode AlGaN/GaN HEMT.

This work investigated the effects of single stress and electro-thermo-mechanical coupling stress on the electrical properties of top-cooled enhancement mode (E-mode) Aluminium Gallium Nitride/Gallium Nitride (AlGaN/GaN) high electron mobility transistor (HEMT) (GS66508T). Planar pressure, linear deformation, punctate deformation, environmental temperature, electro-thermal coupling, thermo-mechanical coupling, and electro-thermo-mechanical coupling stresses were applied to the device. It was found that different kinds of stress had different influence mechanisms on the device. Namely, excessive mechanical pressure/deformation stress caused serious, irrecoverable degradation of the device's leakage current, with the gate leakage current (Ig) increasing by ~107 times and the drain-to-source leakage current (Idss) increasing by ~106 times after mechanical punctate deformation of 0.5 mm. The device characteristics were not restored after the mechanical stress was removed. Compared with three mechanical stresses, environmental thermal stress had a greater influence on the device's transfer characteristic and on-resistance (Ron) but far less influence on Ig and Idss. As was expected, multiple stress coupled to the device promoted invalidation of the device. For more in-depth investigation, finite element simulation carried out with COMSOL was used to analyze the effect of electro-thermo-mechanical coupling stress on top-cooled E-mode AlGaN/GaN HEMT. The results of the experiments and simulation demonstrated that single and coupled stresses, especially mechanical stress coupled with other stresses, degraded the electrical properties or even caused irreversible damage to top-cooled E-mode AlGaN/GaN HEMT. Mechanical stress should be reduced as much as possible in the packaging design, transportation, storage, and application of top-cooled E-mode AlGaN/GaN HEMT.

Integrating a Soft Body Diode in the Super-Junction MOSFET by Using an n-/n+-Buffer Layer.

In this paper, a novel silicon super-junction (SJ) MOSFET embedded with a soft reverse recovery body diode is proposed and studied by numerical simulation. The device introduces an n+-buffer layer between the n--buffer layer and the n+-substrate to improve the reverse recovery behaviour of its body diode. The n+-buffer layer provides residual carriers during the reverse recovery process, reduces the overshoot voltage, and suppresses oscillation. Simulated results demonstrate that the increment of the on-resistance and the drain-to-source overshoot voltage can be respectively kept below 5% and 20 V, if a 10 µm n+-buffer layer whose impurity concentration ranges from 4 × 1015 cm-3 to 6 × 1016 cm-3 is used. In addition, the fabrication process is the same as that of the conventional SJ-MOSFET. These features make the proposed SJ-MOSFET suitable for inverter applications.

TCAD-Based Investigation of a 650 V 4H-SiC Trench MOSFET with a Hetero-Junction Body Diode.

In this paper, a 650 V 4H-SiC trench Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) with a hetero-junction diode (HJD) and double current spreading layers (CSLs) is proposed and studied based on Sentaurus TCAD simulation. The HJD suppresses the turn-on of the parasitic body diode and improves the performance in the third quadrant. CSLs with different doping concentrations help to lower the on-state resistance as well as the gate-drain capacitance. As a result, the on-state resistance is decreased by 47.82% while the breakdown voltage remains the same and the turn-on and turn-off losses of the proposed structure are reduced by 83.39% and 68.18% respectively, compared to the conventional structure.

A Novel AlGaN/Si3N4 Compound Buffer Layer HEMT with Improved Breakdown Performances.

In this article, an AlGaN and Si3N4 compound buffer layer high electron mobility transistor (HEMT) is proposed and analyzed through TCAD simulations. In the proposed HEMT, the Si3N4 insulating layer is partially buried between the AlGaN buffer layer and AlN nucleating layer, which introduces a high electric field from the vertical field plate into the internal buffer region of the device. The compound buffer layer can significantly increase the breakdown performance without sacrificing any dynamic characteristics and increasing the difficulty in the fabrication process. The significant structural parameters are optimized and analyzed. The simulation results reveal that the proposed HEMT with a 6 µm gate-drain distance shows an OFF-state breakdown voltage (BV) of 881 V and a specific ON-state resistance (Ron,sp) of 3.27 mΩ·cm2. When compared with the conventional field plate HEMT and drain connected field plate HEMT, the breakdown voltage could be increased by 148% and 94%, respectively.

SiC Heterojunction Trench MOSFET with a Buried P-Type Pillar for the Low Gate-Drain Charge and Switching Loss.

A novel Silicon-Carbide heterojunction U-MOSFET embedded a P-type pillar buried in the drift layer (BP-TMOS) is proposed and simulated in this study. When functioning in the on state, the merged heterojunction structure will control the parasitic body diode, and the switching loss will decrease. Moreover, to lighten the electric field on the gate oxide corner, a high-doped L-shaped P+ layer near the heterojunction beneath the gate oxide was introduced; thus, the gate oxide reliability improved. A p-type pillar is introduced in the drift layer. The p-type pillar can assistant the drift layer to deplete. Thus, the specific on-resistance for BP-TMOS can be reduced with an increase in the N-drift region's doping concentration. Compared to the traditional SiC MOSFET (C-TMOS), the specific on-resistance decreased by 20.4%, and the breakdown voltage increased by 53.7% for BP-TMOS, respectively. Meanwhile the device exhibits a 55% decrease and a 69.7% decrease for the switching loss and gate to drain charge.

A Noise-Reduced Light-to-Frequency Converter for Sub-0.1% Perfusion Index Blood SpO[Formula: see text] Sensing.

To improve the SpO 2 sensing system performance for hypoperfusion (low perfusion index) applications, this paper proposes a low-noise light-to-frequency converter scheme from two aspects. First, a low-noise photocurrent buffer is proposed by reducing the amplifier noise floor with a transconductance-boost ( gm-boost) circuit structure. Second, a digital processing unit of pulse-frequency-duty-cycle modulation is proposed to minimize the quantization noise in the following timer by limiting the maximum output frequency. The proposed light-to-frequency sensor chip is designed and fabricated with a 0.35- µm CMOS process. The overall chip area is 1 × 0.9 mm 2 and the typical total current consumption is about 1.8 mA from a 3.3-V power supply at room temperature. The measurement results prove the proposed functionality of output pulse duty cycle modulation, while the SNR of a typical 10-kHz output frequency is 59 dB with about 9-dB improvement when compared with the previous design. Among them, 2-3 dB SNR improvement stems from the gm-boosting and the rest comes from the layout design. In-system experimental results show that the minimum measurable PI using the proposed blood SpO 2 sensor could be as low as 0.06% with 2-percentage-point error of SpO 2. The proposed chip is suitable for portable low-power high-performance blood oximeter devices especially for hypoperfusion applications.

A Low Power and Fast Tracking Light-to-Frequency Converter With Adaptive Power Scaling for Blood SpO 2 Sensing.

This paper presents a monolithic low power and fast tracking light-to-frequency converter for blood SpO 2 sensing. Normally, the tracking speed and the power consumption are two contradictory characteristics. However, different gain-bandwidth specifications for various ambient light intensities allow the dynamic optimization of the power consumption according to the light intensity. In this paper, the amplifier power consumption is adaptively scaled by the generated light-intensity-positively-correlated control voltage. Thus, the chip total power consumption at low light intensity is significantly decreased. Moreover, the proposed adaptive power scaling is achieved with a continuous analog domain, which does not introduce extra switching noise. The proposed light-to-frequency sensor chip is fabricated by using 0.35  µm CMOS technology with a die area of 1 × 0.9 mm 2. The measurement results show that the pulse light response for any light intensity is no longer than two new output square-wave cycles. The maximum total current consumption is 1.9 mA from a 3.3 V supply voltage, which can be adaptively scaled down to only 0.7 mA if the output frequency is about 25 KHz or lower. The minimum operational supply voltage of the proposed sensor chip is 2.5 V in the temperature range of -25 to 80  °C with 4 KV ESD level (human-body model).

A Spatial-Temporal Method to Detect Global Influenza Epidemics Using Heterogeneous Data Collected from the Internet.

The 2009 influenza pandemic teaches us how fast the influenza virus could spread globally within a short period of time. To address the challenge of timely global influenza surveillance, this paper presents a spatial-temporal method that incorporates heterogeneous data collected from the Internet to detect influenza epidemics in real time. Specifically, the influenza morbidity data, the influenza-related Google query data and news data, and the international air transportation data are integrated in a multivariate hidden Markov model, which is designed to describe the intrinsic temporal-geographical correlation of influenza transmission for surveillance purpose. Respective models are built for 106 countries and regions in the world. Despite that the WHO morbidity data are not always available for most countries, the proposed method achieves 90.26 to 97.10 percent accuracy on average for real-time detection of global influenza epidemics during the period from January 2005 to December 2015. Moreover, experiment shows that, the proposed method could even predict an influenza epidemic before it occurs with 89.20 percent accuracy on average. Timely international surveillance results may help the authorities to prevent and control the influenza disease at the early stage of a global influenza pandemic.

DANoC: An Efficient Algorithm and Hardware Codesign of Deep Neural Networks on Chip.

Deep neural networks (NNs) are the state-of-the-art models for understanding the content of images and videos. However, implementing deep NNs in embedded systems is a challenging task, e.g., a typical deep belief network could exhaust gigabytes of memory and result in bandwidth and computational bottlenecks. To address this challenge, this paper presents an algorithm and hardware codesign for efficient deep neural computation. A hardware-oriented deep learning algorithm, named the deep adaptive network, is proposed to explore the sparsity of neural connections. By adaptively removing the majority of neural connections and robustly representing the reserved connections using binary integers, the proposed algorithm could save up to 99.9% memory utility and computational resources without undermining classification accuracy. An efficient sparse-mapping-memory-based hardware architecture is proposed to fully take advantage of the algorithmic optimization. Different from traditional Von Neumann architecture, the deep-adaptive network on chip (DANoC) brings communication and computation in close proximity to avoid power-hungry parameter transfers between on-board memory and on-chip computational units. Experiments over different image classification benchmarks show that the DANoC system achieves competitively high accuracy and efficiency comparing with the state-of-the-art approaches.